-
I
DDQ
became popular in the late 1980s as an alternative strategy to detect Stuck-At and non-Stuck-At faults.
-
I
DDQ
before and after provoking the fault.
-
Subthreshold Conduction
-
The transistor is partially conducting for voltages below the threshold voltage.
-
The region is referred to as
weak-inversion
.
-
Right logarithmic plot shows current decays in an exponential fashion.
-
Threshold current increases with scaling due to threshold voltage scaling and short-channel effects such as DIBL and punch-through.
-
This increases the mean and variance of I
DDQ
.
-
Conceptionally simple:
-
Apply the test pattern and wait for the transients to settle.
-
Compare the static current against a threshold.
-
Current measurements can be performed
on-chip
or
off-chip
by current probes with the following design heuristics:
-
Easily placed between the CUT and the bypass capacitor at the power supply pin.
-
Sensitive to very small currents.
-
Nonintrusive: it does not cause an IR drop exceeding a few tens of mV.
-
Capable of fast measurement (no more than 500ns).
-
Need to provide a sensing structure that
-
Bypasses the transient.
-
Compensates for the IR drop.
-
Op amp designed such that it compensates for the IR drop across the probe resistor.
-
Alternatively, a
diode
or
transistor
can be used:
-
Transistor turned on during the transient.
-
A structure that
eliminates the resistor
altogether.
-
Again, the transistor is turned on long enough to pass the transient.
-
Afterwards, the transistor is turned off and the current
strobed
.
-
During this time, the quiescent current is supplied by C
bp
.
-
where
delta t
is the time necessary for the transient to subside.
-
To get 25 uA/10mV in 500ns, C
bp
= 1,250pF.
-
To limit the drop to 1V (under 5V), the current strobe must be done before t = 50ms.
-
Built-In Current (BIC) sensors
-
Main advantage is increased speed and resolution.
-
Basic idea is to insert a
voltage drop device
between the DUT's ground and the chip's GND.
-
The comparator fails the chip if V
GND > Vref.
-
The
voltage drop device
can be linear or non-linear (transistor).
-
Detecting a fault requires a test that creates a conducting path between V
DD
and GND.
-
The test patterns required to activate these faults are equivalent to stuck fault patterns that guarantee the propagation of the fault to the
gate output
.
-
These patterns are called
psendo-stuck-at
patterns.
-
I
DDQ
tests shown to detect
stuck-at
,
stuck-on
,
bridging
and some types of
stuck-open faults
.
:
|
Defect
|
SAF
|
IDDQ
|
|
GOS
|
Rarely
|
Yes
|
|
Punchthrough
|
Rarely
|
Yes
|
|
Leaky junctions
|
Rarely
|
Yes
|
|
Parasitic leaks
|
Rarely
|
Yes
|
|
Shorts to rails
|
Yes
|
Yes
|
|
Open drain or source
|
No
|
Sometimes
|
|
Open gate with Vin>Vth
|
Yes
|
No
|
|
Transmission gate
|
No
|
Yes
|
|
Resistive bridge
|
No
|
Yes
|
-
I
DDQ
uncovers defects that cause
leakage current
regardless of the fault model.
-
Leakage faults:
-
The leakage fault model includes
six
leakage faults per MOS transistor.
-
These are the leakage paths between any combination of its 4 terminals, e.g. F
gs
is leakage between the
gate
and
source
, etc.
-
Stuck-ons
are F
ds
leakage faults between the
source
and
drain
.
-
Provoking the F
gs
requires
AC
=
0x
while F
gd
requires
AC
=
10
.
-
Switch-level
TPG strategy uses a
connection graph
.
-
To generate patterns for
stuck-on
and
stuck-open
transistors, all paths are traced from the output node to V
DD
and GND.
-
To check for a short in the
n-network
, apply a
0
to the tested node and
1
s to other series connected nodes (and
0
s to parallel nodes).
-
Switch-level approach is good for
SON
and
SAF
faults but not other types of shorts.
-
Leakage
TPG strategy uses a
gate-level
hierarchical representation.
-
Each cell is analyzed under all possible input/output combinations and the leakage faults detected under each pattern are recorded in a table:
-
Leakage
TPG strategy:
-
The circuit is then logic simulated using
functional test
patterns.
-
The
current testing
patterns are selected using the logic simulation values and the lookup table for each gate.
-
Experiments have shown that only
1%
of the functional test patterns are needed for good fault coverage.
-
Impact of Deep-Submicron Technology:
|
Technology
|
VDD(V)
|
Tox(A)
|
Vt(V)
|
Leff(um)
|
Ioff(pA/um)
|
|
1.0
|
5
|
200
|
|
0.8
|
0.00041
|
|
0.8
|
5
|
150
|
0.60
|
0.55
|
0.00058
|
|
0.6
|
3.3
|
80
|
0.58
|
0.35
|
0.15
|
|
0.35
|
2.5
|
60
|
0.47
|
0.25
|
8.9
|
|
0.25
|
1.8
|
45
|
0.43
|
0.15
|
24.0
|
|
0.18
|
1.6
|
30
|
0.40
|
0.10
|
86.0
|
-
Last column give I per unit length. (Last two rows are only estimates.)
-
As we know, as the defect-free I
off
increases, M
g
- M
d
is reduced.
-
Different mechanisms are responsible for leakage at different technology nodes.
-
For example, reverse-biased
pn
-juniction leakage current was dominant for technologies > 1um.
-
As we know,
subthreshold
leakage is dominant for technologies < 0.5um.
-
For example, reducing V
t
by 50% results in
3 orders
of magnitude increase!
-
Anne Gattiker was the first to propose a non-single threshold technique (
Current Signatures
).
-
Here, a signature is created by ordering all the measurements by magnitude.
-
Maxwell proposed
Current Ratios
in ITC 1998.
-
ITRS review considered the following as possible solutions:
-
Use of Delta I
DDQ
or I
DDQ
Ratios test methods.
-
Substrate biasing to control V
t.
-
Processing changes to have higher V
t
(either for all devices or selected ones) or lower V
t
variance.
-
I
DDQ
testing at low temperature.
-
Power supply partitioning at chip level. Use of multiple power sources.
-
Use of large "footer" devices that limit leakage currents in the transistor path.
-
I
DDQ
measurements for multiple V
DD
voltages.
-
I
DDT
techniques.
-
I
DDQ
limits determined based on comparisons with neighboring die.
-
I
DDQ
measured simultaneously on a set of power supply pads.
-
Built-in I
DDQ
sensors (potentially self-calibrating) or other on-chip measurement aids.
