Modeling

• Design Representations vs. Design Specifications:
• Design specifications describe the design in terms of its results.
• Design models describe the structure and behavior of the design.

 

• Domains and Level of Design :

Level of Abstraction	Domain
	Behavioral	Structural	Physical
System	System Specifications	Blocks	Chip
RTL	RTL Specifications	Registers	Macro cells
Logic	Boolean Functions	Logic Gates	Standard Cells
Circuit	Differential Equations	Transistors	Masks

 

• At any given level, the design may be described using equations, tables or HDLs.

Boolean Difference

• Makes use of Shannon Expansion :

 

• Repeated application to a function f results in the DNF of the function.
• The residue of the function for x _i = 1 is its value when x _i is set to 1.

 

• For example:

Boolean Difference

• Switching functions (a special case of Boolean functions) are used in TPG.
• For example, to observe a stuck fault, the response of the good circuit, R , must be different than that of the bad circuit, R _f .

• For nodes x _i at the PIs, R and R _f are the residuals of the function w.r.t. x _i .

 

• Rewriting the above expression as a Boolean difference w.r.t. xi :

• Equating this to 1 determines the values of the variables that allow the observability of the fault on node x _i at the PO.

 

• x _i = 0 is needed to detect an SA1 and x _i = 1 is needed to detect an SA0 .

Boolean Difference

• For example:

• Consider faults on the PI, x ₂ .

• which implies that x ₁ = 1 and x ₃ = 0.

 

• For the SA1 test, set the product of x ' ₂ and the Boolean difference to 1.
• For the SA0 tests set the product of x ₂ and the Boolean difference to 1.

• Unfortunately, this method is not computationally efficient for TPG.

Finite State Machines

• Formally expressed as a six-tuplet (I, S, d, S ₀ , O, l )
• I and O is the input/output alphabet.
• S _{0 (start states)} , are a subset of S.
• d: S X I -> S (next-state function), l : S X I -> O (output function, Mealy)
• A table representation of an FSM.

State/Input x	0	1
1	2,1	3,0
2	2,1	4,0
3	1,0	4,0
4	3,1	3,0

• Asynchronous Sequential Circuits (no clocks) represented by a Flow Table.

	00	01	11	10
1	1,0	5,1	2,0	1,0
2	1,0	2,0	2,0	5,1
3	3,1	2,0	4,0	3,0
4	3,1	5,1	4,0	4,0
5	3,1	5,1	4,0	5,1

Truth Tables and Cubes

• The simplest way to represent a combinational circuit is by its truth table :

x1	x2	x3	Z
0	0	0	1
0	0	1	1
0	1	0	0
0	1	1	1
1	0	0	1
1	0	1	1
1	1	0	0
1	1	1	0

• A data structure representing the truth table is usually an array V of dimension 2 ⁿ , with the inputs arranged in increasing binary order.
• A simple method to find the value of Z is to concatenate the input values.

 

• The truth table shown previously can be represented in a compact representation via Primitive Cubes.
• Cubical notation for the first two rows of the truth table is 00x|1 .

Truth Tables and Cubes

• An implicant g of Z (x ₁ , x ₂ , x ₃ ) is converted to a cube ( v ₁ v ₂ v ₃ | v _Z ) by:
• Setting v _i to 1(0) , if x _i ( x _i ) appears in g .
• Setting v _i to x , if neither x _i nor x _i appears in g .
• Setting v _Z to 1 for v _Z = Z (v ₁ , v ₂ , v ₃ ).
• For example, implicant x1x2 converts to 00x|1 .

 

• If cube q can be obtained from cube p by replacing one or more x values in p by 0 or 1 , we say p covers q .
• For example, cube 00x|1 covers cubes 000|1 and 001|1 .

 

• A cube representing a prime implicant of Z or Z is called a primitive cube .

Truth Tables and Cubes

• We can then use the primitive cube representation to determine the value of an input combination, by finding an entry that covers it:
• For example, ( v ₁ v ₂ v ₃ ) = 010 matches the primitive cube x10|0 .
• Therefore, Z (010) = 0 .

 

• The matching operation is implemented by the intersection operator:

&&	0	1	x
0	0	empty	0
1	empty	1	1
x	0	1	x

• The intersection of 0 and 1 is inconsistent .
• The intersection of two cubes is consistent iff all the corresponding values are consistent or compatible .

 

• Primitive cubes provide a compact representation and can help in TPG.
• For example, if we seek Z = 1 , we need either x ₂ = 0 or x ₁ x ₃ = 01 .

Graphical Representations

• A graph G ( V , E , W ) is defined as:
• V : vertices or nodes
• E : edges
• W : weights
• An directed edge e ( u , v ) is used in a directed graph.

• Other standard definitions:
• An undirected graph is a symmetric directed graph.
• A path is a sequence of edges.
• A connected graph if there is a path from one edge to every other edge.
• A cycle is a closed path of some length.
• A complete graph has an edge between every pairing of nodes.

Graphical Representations

• Binary Decision Diagrams (BDDs):
• They are directed acyclic graphs (DAGs).

 

• The vertices are partitioned into three sets:
• Root ( in-degree = 0, out-degree = 2)
• Internal nodes ( in-degree = 1, out-degree = 2)
• Both of these represent variables of the function.

 

• Leafs ( in-degree = 2, out-degree = 0)
• The values of the leaf vertices are 0 and 1.

 

• The edges of the graph represent the literal alternatives (0 or 1) for these variables.

 

• Evaluation of an expression involves traversing the graph.
• Finding all paths to 1 yields the products of f .

Binary Decision Diagrams

• BDDs can be developed by recursively applying the Shannon expansion.
• Let's start with variable x 1 with f(x1, x2) = x 1 x 2
• The successors of x 1 are the residues of the f for x 1 = 0 and x 1 = 1

• In this case, the function is symmetrical and the same diagram is obtained if x ₂ was the starting variable.
• However, in general, the diagram is sensitive to the order in which the variables are considered.

 

• Algorithms to generate BDDs are of order O(2 ^N /N).

Binary Decision Diagrams

• TPG application:

• The output of the good circuit is 0(1) and of the faulty circuit 1(0).
• Procedure : Trace from root to each of 0 and 1 leaf nodes.
• Rules : Nodes common on both traces must be the same value .

 

• The corresponding values of the variables constitute the test.

RTL Behavioral Modeling

• RTLs provide models for systems at the register and instruction set levels.

 

• Data is stored in:
• Registers

register IR[0->7]

• Memories organized as arrays of registers

memory MEM[0->256; 0->15]

 

• RTL models are characterized as behavioral (only provide some structural information).

 

• Primitive operators ("+" and "=") are used to transform and transfer data.

C = A + B

 

• Conditional operators are also defined.

if X then C = A + B

if (CLOCK and (AREG < BREG)) then AREG = BREG

RTL Behavioral Modeling

• Higher level language constructs are also available, such as if...then....else and case statements.

test (IR[0->3])

case 0: operation0

case 1: operation1

...

case 15: operation15

testend

 

• RTLs also provide compact constructs to address memory.

MEM[BASEREG + PC]

 

• Combinational functions can be directly described by Boolean operators.

Z = (A and B) or C

 

• Other primitive operators include shift and count.

shift_right(AREG, 2, 0)

incr (PC)

RTL Behavioral Modeling

• Some RTLs allow references to past values of variables, for example, to model the rising edge of a clock signal, X .

if (X(-1)=0 and X=1) then ...

 

• Finite state machines modeling.

state S1, S2, S3

 

S1: if X then

begin

P = Q + R

go to S2

end

else

P = Q - R

go to S3

S2: ...

Timing Models for RTLs

• There are two catagories, depending on the treatment of the concept of time.
• Procedural languages
• Similar to conventional programming languages where statements are executed sequentially, e.g., C gets new value of A .

A = B

C = A

 

• Non-procedural languages
• Statements are executed in parallel, e.g., exchanges A and B .

A = B

B = A

 

• Procedural RTLs are usually used to describe a system at the instruction set level of abstraction, which uses an implicit cycle-based timing model, e.g.,
• Fetch, decode, execute phases.

 

• Timing information can be specified in the behavior model.

C = A + B, delay = 100

• Some RTLs allow a mixture of procedural and non-procedural constructs.

Other Representations

• Read text description of netlists and HDLs (verilog and VHDL).

 

• Note that these representations ( truth tables , state tables or BDDs ) are data structures interpreted by model-independent programs.

 

• An alternative is a code-based model ( compiled-code model) .
• For speed, the circuit can be modeled by a program directly.