Overview

Overview

As we have seen, sequential circuit testing is complex and time consuming.

Scan proposed in '73 by Williams and Angell.

It facilitates the initialization, controllability and observability.

It reduces sequential TPG to combinational TPG.

With Scan, a synchronous sequential circuit works in two modes.

Normal mode and test mode:

Overview

In test mode , all FFs are disconnected from the CUT and configured as a shift register.

They are easily initialized and can be used as pseudo-PIs to the CUT.

Once initialized, normal mode is used to apply a pattern to the PIs, and the results are latched in the FFs.

The circuit is put in test mode again and the results scanned out.

Here, the inputs to the FFs act as observation points ( pseudo-POs ).

Scan-Path Design

Any sequential circuit may be modeled as:

TPG

Test pattern generation assumes:
No asynchronous signals (including set and reset of the FFs).
Latches are controlled by non-overlapping clocks.
FF inputs are treated like POs.
FF outputs are treated like PIs.

The number of PIs is then N + M (real and pseudo).

Also, the pseudo-PIs/POs are dispersed , improving observability/controllability, effectively partitioning the CUT into smaller circuits.

The two partitions: G ₁ (pseudo-PI Y ₁ ) and G ₂ /G ₃ (pseudo-PIs Y ₁ / Y ₂ ).

Test Pattern Application

The FFs are tested first followed by the combinational part.

The FFs are configured as a shift register ( SE =1) and a pattern of 1s and 0s are applied to the SI input.

Testing the combinational part consists of:
Set SE =1, shift in the initial values on the FF for the first pattern.

Repeat for all patterns
Set SE =0, apply a pattern to the PIs.
Clock the circuit once to latch internal values, observe the POs.
Set SE =1, scan out the rest of the results
Scan in the initialization pattern for the next sequence.
End repeat

M clocks ( M is the number of FFs) are needed for each iteration!

Test Pattern Application

Our example circuit has two partitions:
Partition 1 has inputs F and y ₂ with output D ₁ .
Partition 2 has inputs F, y ₁ and y ₂ with outputs D ₂ and Z.

The three XOR gates can be tested simultaneously.

Test Pattern Application

Although only 3 patterns are necessary, let's use an exhaustive test FY ₁ = 00, 10, 01, 11, and FY ₁ Y ₂ = 000, 100, 011, 111.

We first test the FFs using a sequence of 1s followed by 0s.

Note, pattern sensitive FF faults should be tested using alternating 1s and 0s.

Clk	SE	F	SI	PS y1y2	NS Y1Y2	Z	SO
1	1	x	1	xx	1x	x	x
2	1	x	1	1x	11	x	xx
3	1	x	0	11	01	0	1xx
4	1	x	0	01	00	1	11xx
5	1	x	0	00	00	0	011xx
6	0	0	x	00	D1D2	0	Z011xx

Clks 1-4 set up the FFs for the first test, 00 on G ₁ and G ₂ ( Fy ₁ =00, Fy ₂ =00).
Clks 5-6 serve to let us verify the 00 holding capability of the FF while simultaneously applying the first pattern.

Test Pattern Application

Now we need to clock twice to observe the response of the first test (Clks 7-8).
Clk 9 applys the second test, Fy ₁ y ₂ =100 and Clks 10-11 observe the response and initialize for the next test Fy ₁ y ₂ =011.

Clk	SE	F	SI	PS y1y2	NS Y1Y2	Z	SO
7	1	x	0	D1D2	0D1	x	D20011xx
8	1	x	0	0D1	00	x	D1D20011xx
9	0	1	x	00	D1D2	1	ZD1D20011xx
10	1	x	1	D1D2	1D1	x	D2ZD1D20011xx
11	1	x	1	1D1	11	x	D1D2ZD1D20011xx
12	0	0	x	11	D1D2	0	ZD1D2ZD1D20011xx
13	1	x	1	D1D2	1D1	x	D2ZD1D2ZD1D20011xx
14	1	x	1	1D1	11	x	D1D2ZD1D2ZD1D20011xx
15	0	1	x	11	D1D2	1	ZD1D2ZD1D2ZD1D20011xx
16	1	x	z	D1D2	aD1	x	D2ZD1D2ZD1D2ZD1D20011xx
17	1	x	b	aD1	ba	x	D1D2ZD1D2ZD1D2ZD1D20011xx

Clks 12-14 apply/observe Fy ₁ y ₂ =011, Clks 15-17 apply/observe Fy ₁ y ₂ =111.

Storage Cells for Scan Designs

Common characteristics of all designs:
A normal input and a scan input .

The appropriate input can be selected using a multiplexer or by a two-clock system.

A storage cell .

The cell can be implemented using an edge-triggered FF, a master-slave FF or level-sensitive latches controlled by clocks having >=2 phases.

We'll focus only on D-FFs of the master-slave variety.

Storage Cells for Scan Designs

An implementation using two-port master-slave FF with a MUX .

A two-port clocked FF implementation.

Storage Cells for Scan Designs

To ensure race-free operation, use a 2-phase nonoverlapping clk.

In order to avoid performance degradation introduced by the MUX.

Storage Cells for Scan Designs

In LSSD, clocks f₁ and f₂ can be NORed together to drive L ₂ , replacing f₃ .

Note that in the 3-clock scheme, in order to prevent hazards, f₁ and f₃ and well as f₂ and f₃ MUST be non-overlapping.

Scan Architectures

General structure of an LSSD double-latch design.

The outputs, y _i , come from the output of the L ₂ latches.
Normal mode, f₁ and f₃ are used, test mode, f₂ and f₃ are used.

Scan Architectures

In pipelined systems, combinational blocks are separated by only 1 latch .

Scan Architectures

During normal mode, f_1a and f_1b are nonoverlapping clocks, and clocks f₂ and f₃ are not used.

Note that L ₂ are not used during normal operation and represents overhead.

For the double latch design, operation proceeds as follows:
Test the latches:

Set f₂ = f₃ =1.

Apply 0 and 1 alternatively at SI
Clock f₂ , then f₃ , n times.
Initialize:

Shift in the initial values into the FFs.

Repeat for all patterns:

Apply a pattern to the PIs.
Clock f₁ , then f₃ and observe results at POs.
Shift out the response and initialize for next pattern.

Clock f₂ , then f₃ , n times.

Scan Architectures

Scan-Set Architecture offers on-line test capability.

TClk and SI used to initialize FFs with SE ₁ / SE ₂ =1, then SClk used to load data into upper FFs in parallel.
Test pattern applied to PIs, SE ₁ / SE ₂ =0, then SClk transfers data to upper FFs, TClk used to scan data out.