LAB Assignment #3 for CMPE 413/CMSC 711
Assigned: Friday, Sept 22th
Due: Friday, Sept 29th
Description: Simulate using Spectra the Inverter, OAI and XNOR/XOR gate layouts from the previous two labs:
Follow the instructions on my web page (Laboratory Notes section) to update your cds.lib file and to add the MOS models.
In Virtuoso, you need to create a new view (extracted view) of each gate.
Be sure to add PINS to all inputs, outputs and sources (Vdd and GND). Spectra will allow you to access these pins in its dialogs. Labels will NOT work.
The laboratory instruction should get you started with the Spectra tool. Please refer to the OpenBook documentation for additional details on the simulator. We will try to get a tutorial put together on these tools next week but don't wait for it, start now.
1) Briefly describe the steps required to prepare the layout and simulator (as outlined above). More details can be added as you see fit. Remember, your report should allow another student to reproduce your results.
2) Run simulations showing functionality of these gates (e.g. show that they compute the correct logic function). Generate plots for some of these simulations for each gate.
3) Run simulations to determine the worst and best case delays through the XNOR and OAI gates. In other words, which input transitions (e.g. changing A from 1 to 0 and B from 0 to 1) cause the largest and smallest delay through these gates. Generate plots showing these cases for both gates. Measure delay at the 50% point between the input transition and output transition.
4) Grading will be based on the completeness of your write-up.