LAB Assignment #3 for CMPE 413/CMSC 711

Assigned: Friday, Sept 22th

Due: Friday, Sept 29th

Description: Simulate using Spectra the Inverter, OAI and XNOR/XOR gate layouts from the previous two labs:

Report Requirements:

1) Briefly describe the steps required to prepare the layout and simulator (as outlined above). More details can be added as you see fit. Remember, your report should allow another student to reproduce your results.

2) Run simulations showing functionality of these gates (e.g. show that they compute the correct logic function). Generate plots for some of these simulations for each gate.

3) Run simulations to determine the worst and best case delays through the XNOR and OAI gates. In other words, which input transitions (e.g. changing A from 1 to 0 and B from 0 to 1) cause the largest and smallest delay through these gates. Generate plots showing these cases for both gates. Measure delay at the 50% point between the input transition and output transition.

4) Grading will be based on the completeness of your write-up.