LAB Assignment #5 for CMPE 413/CMSC 711

Assigned: Friday, Oct 13th

Due: Friday, Oct 20th

Description: Use Composer to construct transistor level schematic diagrams for the layouts of labs 1 through 4 and LVS to verify they are consistent with the layouts.

The layouts that you have done so far are:

Lab #1: The Inverter.

Lab #2: The OAI and XNOR or XOR.

Lab #4: The Transmission-gate master-slave flip-flop and a gate-level version.


1) For each of these 5 layouts, construct a transistor-level schematic diagram (using the nmos4 and pmos5 library components). For each schematic and layout, use LVS to verify that they are electrically equivalent.

2) For one of these schematics, run a functional simulation using Spectra.

Report Requirements:

1) Print out the schematics.

2) Run LVS on the schematic against the layout, as demonstrated in lab.

3) Print out the output file (button from main LVS window) showing the status of the schematic to layout verification for each of the 5 schematic/layout gates.

4) For ONLY one of the gates (your choice), run a functional simulation from Composer. Print out the input and output waveforms.

5) As always, grading will be based on the completeness of your write-up so be sure to describe the objectives of the lab, the procedure you followed to complete it and the results.