Checking out license 'RTL_Compiler_Physical'... (0 seconds elapsed) License RTL_Compiler_Physical checkout failed Checking out license 'RTL_Compiler_Ultra'... (0 seconds elapsed) Reading GUI preferences file '/home/jimp/.cadence/rc.gui'. Cadence Encounter(R) RTL Compiler Version v09.10-p104_1 (32-bit), built Jun 18 2009 Copyright notice: Copyright 1997-2009 Cadence Design Systems, Inc. All rights reserved worldwide. Patent notices: Protected by U.S. Patents: 5892687; 6470486; 6772398; 6772399; 6807651; 6832357; 7007247 ================================================================================================================================================ Welcome to Cadence Encounter(R) RTL Compiler Here is a quick introduction on how to access our product information. If you do not want this message to appear in the future, create an initialization file (an empty file will do) in your home directory called '~/.cadence/.synth_init'. To access the product documentation in HTML and PDF, type 'cdnshelp' at the system prompt. For a list of available commands, type 'help'. To view a man page for a command, type 'man '. To view a man page for an error message, type 'man '. For a list of all possible object types, type 'get_attribute -help'. For a list of all available attributes by object type, type 'get_attribute * -help'. For a list of all attributes for every object type, type 'get_attribute * * -help' To list only writable attributes, substitute 'get_attribute' with 'set_attribute'. To get a template script to run RTL Compiler, use the 'write_template' command. To get a template script to run Conformal based on the current RTL Compiler session, use the 'write_do_lec' command. Obsolete attributes in the current tool version. To learn more, type 'get_attribute -help '. object attribute ------ --------- design checkpoint_dofile_naming_style design checkpoint_netlist_naming_style design dp_perform_rewriting_operations design multipass_mux_optimization design timing_driven_muxopto instance black_box instance dft_inherited_dont_scan instance write_positional_connections libcell black_box net logic0_driven net logic1_driven root bit_blast_constants root bit_blast_mapped_ports root checkpoint_flow root checkpoint_gzipped_netlist root degenerate_complex_seqs root delayed_pragma_commands_interpreter root dp_perform_rewriting_operations root dp_perform_sharing_operations root exact_match_seqs_async_controls root gen_no_negative_index root gen_unconnected_port_style root gen_write_empty_module_for_logic_abstract root hdl_array_generator root hdl_flatten_array root hdl_old_reg_naming root hdl_record_generator root hdl_reg_naming_style_scalar root hdl_reg_naming_style_vector root hdl_trim_target_index root hdl_vector_naming_style root lbr_async_clr_pre_seqs_interchangable root pqos_virtual_buffer root retime_preserve_state_points root wlec_env_var root wlec_flat_r2n root wlec_new_hier_comp root wlec_no_exit root wlec_save_ssion root wlec_sim_lib root wlec_sim_plus_lib root wlec_verbose subdesign allow_sharing_subdesign subdesign dp_perform_rewriting_operations subdesign multipass_mux_optimization subdesign timing_driven_muxopto Send us feedback at rc_feedback@cadence.com. ================================================================================================================================================ rc:/> Setting attribute of root '/': 'hdl_vhdl_environment' = common Setting attribute of root '/': 'hdl_vhdl_read_version' = 1993 Setting attribute of root '/': 'hdl_vhdl_case' = original Setting attribute of root '/': 'lib_search_path' = /home/jimp/cadence_IBM_9rf/ELC/ Setting attribute of root '/': 'library' = std_cells.lib Setting attribute of libcell 'MUXD_DFF_P_X1': 'preserve' = false Setting attribute of libcell 'MUXD_DFF_P_X1': 'avoid' = false Setting attribute of root '/': 'hdl_track_filename_row_col' = true Elaborating top-level block 'CNTER_8BIT_SCAN' from file 'CNTER_8BIT_SCAN.vhd'. Done elaborating 'CNTER_8BIT_SCAN'. Setting attribute of root '/': 'dft_scan_style' = muxed_scan Trying carrysave optimization (configuration 1 of 1) on module 'CNTER_8BIT_SCAN_csa_cluster'... Info : Done carrysave optimization. [RTLOPT-20] : There is 1 CSA group in module 'CNTER_8BIT_SCAN_csa_cluster'... Accepted. Info : Performing pre-map downsize. [RTLOPT-16] : Downsize instance 'inc_ADD_UNS_OP_1' to slow architecture. Mapping CNTER_8BIT_SCAN to gates. Global mapping target info ========================== Cost Group 'default' target slack: Unconstrained Global mapping status ===================== Worst Total Neg Operation Area Slack Worst Path ------------------------------------------------------------------------------- global_map 100 0 N/A Global incremental target info ============================== Cost Group 'default' target slack: Unconstrained Global incremental optimization status ====================================== Worst Total Neg Operation Area Slack Worst Path ------------------------------------------------------------------------------- global_inc 100 0 N/A Worst - - - - DRC Totals - - - - Total Neg Max Max Max Operation Area Slack Trans Cap Fanout ------------------------------------------------------------------------------- init_iopt 100 0 0 0 0 Incremental optimization status =============================== Worst - - - - DRC Totals - - - - Total Neg Max Max Max Operation Area Slack Trans Cap Fanout ------------------------------------------------------------------------------- init_delay 100 0 0 0 0 init_drc 100 0 0 0 0 init_area 100 0 0 0 0 Incremental optimization status =============================== Worst - - - - DRC Totals - - - - Total Neg Max Max Max Operation Area Slack Trans Cap Fanout ------------------------------------------------------------------------------- init_delay 100 0 0 0 0 init_drc 100 0 0 0 0 init_area 100 0 0 0 0 Done mapping CNTER_8BIT_SCAN Synthesis succeeded. Pin or port 'SCAN_IN' not found. Pin or port 'SCAN_OUT' not found. Scan mapping status report ========================== Scan mapping: converting flip-flops that pass TDRC. Scan mapping done: 8 flip-flops mapped to scan. Category Number Percentage ----------------------------------------------------------- Scan flip-flops mapped for DFT 8 100.00% Flip-flops not mapped for DFT flip-flops not scan replaceable 0 0.00% flip-flops not targeted for DFT 0 0.00% ----------------------------------------------------------- Totals 8 100.00% Starting DFT Scan Configuration for module 'CNTER_8BIT_SCAN' in 'normal' mode, with physical flow OFF Configuring 1 chains for 8 scan f/f Configured 1 chains for Domain: 'Clk', edge: 'rising' cnter_scan (SCAN_IN -> SCAN_OUT) has 8 registers; Domain:Clk, edge: rising Processing 1 scan chains in 'muxed_scan' style. Default shift enable signal is 'SCAN_EN': '/designs/CNTER_8BIT_SCAN/ports_in/SCAN_EN' active high. Mapping DFT logic introduced by scan chain connection... Mapping DFT logic done. Checking DFT rules for 'CNTER_8BIT_SCAN' module under 'muxed_scan' style Checking DFT rules for clock pins Checking DFT rules for async. pins Checking DFT rules for shift registers. Detected 0 DFT rule violation(s) Summary of check_dft_rules ************************** Number of usable scan cells: 1 Clock Rule Violations: --------------------- Internally driven clock net: 0 Tied constant clock net: 0 Undriven clock net: 0 Conflicting async & clock net: 0 Misc. clock net: 0 Async. set/reset Rule Violations: -------------------------------- Internally driven async net: 0 Tied active async net: 0 Undriven async net: 0 Misc. async net: 0 Total number of DFT violations: 0 Total number of Test Clock Domains: 1 Number of user specified non-Scan registers: 0 Number of registers that fail DFT rules: 0 Number of registers that pass DFT rules: 8 Percentage of total registers that are scannable: 100% Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'CNTER_8BIT_SCAN'. : Use 'report timing -lint' for more information. ============================================================ Generated by: Encounter(R) RTL Compiler v09.10-p104_1 Generated on: Jan 25 2011 05:42:05 PM Module: CNTER_8BIT_SCAN Technology library: std_cells Operating conditions: typical (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) ----------------------------------------------------------------------- cnter_reg_reg[0]/CLK 0 0 R cnter_reg_reg[0]/Q_B MUXD_DFF_P_X1 2 3.9 104 +128 128 R g132/IN +0 128 g132/OUT INVX1 3 5.1 74 +67 195 F g129/IN2 +0 195 g129/OUT NAND2X1 3 5.8 124 +84 279 R g128/IN +0 279 g128/OUT INVX1 1 2.6 50 +59 338 F g127/IN2 +0 338 g127/OUT NAND2X1 3 5.8 129 +76 414 R g126/IN +0 414 g126/OUT INVX1 1 2.6 51 +60 474 F g124/IN2 +0 474 g124/OUT NAND2X1 3 5.8 129 +77 551 R g123/IN +0 551 g123/OUT INVX1 1 2.6 51 +60 611 F g121/IN2 +0 611 g121/OUT NAND2X1 3 5.8 129 +77 687 R g120/IN +0 687 g120/OUT INVX1 1 2.6 51 +60 747 F g118/IN2 +0 747 g118/OUT NAND2X1 3 5.8 129 +77 824 R g117/IN +0 824 g117/OUT INVX1 1 2.6 51 +60 884 F g115/IN2 +0 884 g115/OUT NAND2X1 3 5.8 129 +77 961 R g114/IN +0 961 g114/OUT INVX1 1 2.6 51 +60 1021 F g112/IN2 +0 1021 g112/OUT NAND2X1 2 4.5 107 +67 1088 R g22/IN +0 1088 g22/OUT INVX2 1 2.5 35 +48 1135 F g20/IN1 +0 1135 g20/OUT NAND2X1 1 2.6 76 +51 1186 R g19/IN2 +0 1186 g19/OUT NAND2X1 1 13.4 172 +109 1295 F cnter_reg_reg[7]/D MUXD_DFF_P_X1 +0 1295 cnter_reg_reg[7]/CLK setup 0 +255 1550 R ----------------------------------------------------------------------- Timing slack : UNCONSTRAINED Start-point : cnter_reg_reg[0]/CLK End-point : cnter_reg_reg[7]/D