Associate Professor, Department of
ECE 595: Advanced VLSI Design
Quality Metrics I (mod:9/9)
Quality Metrics II (mod:9/10)
Fabrication I (mod:9/17)
Fabrication II (mod:9/27)
Diode I (mod:9/27)
MOS I (mod:9/29)
MOS II (mod:9/30)
MOS III (mod:10/11)
Process Variation (mod:10/13)
CMOS Inverter I (mod:11/4)
CMOS Inverter II (mod:11/8)
Combinational Logic I (mod:11/15)
Combinational Logic II (mod:11/17)
Combinational Logic III (mod:11/22)
Combinational Logic IV (mod:11/22)
Sequential Logic I (mod:12/1)
Sequential Logic II (mod:12/6)
Arith I (mod:11/8)
Arith II (mod:11/8)
Mid-term Exam scheduled for Oct 20th.
Sample Midterm (mod:10/18)
Class is cancelled for Wed, Nov 24th.
Final Exam is on Wed. Dec 22 in MP 008 from 6:00 to 8:00 PM -- Chintan will be
proctoring his exam in VLSI testing during this same time/place.
INSTALLING CADENCE at UNM (courtesy of Ryan Helinski)
Start-up files for CADENCE (courtesy of Ryan Helinski)
INSTALLING CADENCE at UNM under Ubuntu 9.10 (courtesy of Mitch Martin)
Since the first six weeks of laboratories are designed to instruct you on basic
layout, simulation and the use of the Cadence tools, these labs are combined
with the undergraduate laboratories. Please refer to http://www.csee.umbc.edu/~cpatel2/
for descriptions of the laboratory assignments.
Class is cancelled on Oct 25 & 27. Optionally, you can attend the undergraduate
class on Monday to see the Silicon Run movie. Chintan's class meets in LH3 at 3:30.
The control sub-groups for each project should plan on meeting in ITC 375 at 11:00am
this Friday, Nov. 12 to discuss the synthesis tools.
For lab #6, tar you vhdl code using 'tar -cvf filename.tar vhdl.files'. Email the
filename.tar file to our TA. Please do this immediately after class today (Nov. 1).
The TA's email address is firstname.lastname@example.org.
OpCodes for 16-bit microprocessor
The PAD FRAME specification that you MUST use and the floorplan of my RISC microprocessor (your floorplan may be different)
My documentation on timing and the PLA for the microprocessor (pdf)
To convert your structural VHDL code to schematic automatically, please follow the instructions
given on Chintan's web page 'http://www.csee.umbc.edu/courses/undergraduate/CMPE413/Fall04/cpatel2/cadence/handouts/import_vhdl.pdf'
For the sub-groups doing the ALU, additional information concerning the BFU, Adder and Shifter
can be found at 'http://www.csee.umbc.edu/courses/undergraduate/CMPE413/Fall04/cpatel2/project/project_fall_2004.pdf'.
I will also put out my arith.pdf slides for easy reference.
For GUI based VHDL simulations, please refer to the last page of Chintan's VHDL tutorial at http://www.csee.umbc.edu/courses/undergraduate/CMPE413/Fall04/cpatel2/cadence/handouts/vhdl.pdf'
DUE 11/8: All standard cells you'll be using in your design. Provide schematic and layout,
and be sure each passes LVS. Simulate them to verify correctness and timing characteristics.
The CIF Pad Frame to be imported
To import, simply bring up the import option under icfb and choose CIF...
Specify the above file as the Input File and risc16_ami as the Top Cell Name.
Add a Library name of your choice and click OK. The cell name is risc16_ami.
You should have a layout view for it. There are some errors that DRC will
report. Please ignore these.