In this project, we designed a test chip for validation of hardware primitives for security and trust and validation of novel embedded test stuctures for measurement and analysis of regional process variations. Cadence tool suite is used for physical design flow and to integrate custom design primitives.

The test chip is designed in IBM CMOS 90nm technology and a total of 70 copies manufactured for statistical analysis. The components of this chip include, various PUF circuits, hardware Trojan detection circuits, embedded test structures for process variations analysis.

This chip has two functional macros, Advanced Encryption Standard (AES) engine and 32-bit pipe-lined floating point unit (FPU). The embedded test structures are integrated with these macros for process variation analysis.

 

The integration of embedded test structures on product chips to measure and analyze delay variations in becoming increasingly important for tracking quality and for improving correlations between hardware and models. Unfortunately, traditional die-to-die level testing and measurement methods, e.g., scribe-line structures, are ineffective for context-sensitive, within-die characterization. More recent efforts to embed test structures, such as distributing a set of ring oscillators across the layout, are capable of capturing within-die variations, but are becoming increasingly less accurate as predictors of delay variations in actual product macros.

In this work, we propose an embedded test structure which is designed to measure the regional path delays in the macros. The proposed structure is capable of measuring the path delays accurately and is minimally invasive as it leverages the existing scan structures in the chip.

The delay measured using this test structure can be used to improve hardware-to-model correlation and hence to ramp-up yield in the production cycle. This test strcture can also be used for delay testing and post-silicon design debug.