Jim Plusquellic is the Director of IC-HAL. He is Associate Professor in Electrical and Computer Engineering Department in University of New Mexico. He is the Co-Founder of International Workshop on Hardware Oriented Security and Trust. He is the Author or Co-Author of more than 85 peer-reviewed Journals and Conference Proceedings. He holds three issued US patents.
Currently, his on going research projects explores Hardware Primitives for Security and Trust and regional Process Variations measurement with minimally invasive Embedded Test Structures.
His research interests are in IC Trust, Design for Manufacturability, Defect-Based Test, e.g., IDDQ/IDDT, Small Delay Fault Test, Model-to-Hardware Correlation and Process Monitors. Personal Website
Charles Lamech is pursuing his PhD in Computer Engineering majoring in Computer Architecture. He holds a Masters degree Electrical Engineering majoring in Applied Electronics and Bachelors degree in Electrical and Electronics Engineering from Anna University, India.
His research focus is Hardware Trojan Detection Analysis and various On-Chip capabilities for side-channel analysis based Trojan Detection.
Currently he is working on an Embedded Test Structure, called REBEL, for measuring combinational path delay of product macros. This is minimally invasive as it leverages existing test structures (Scan Chains) and can be used for Trojan Detection, Delay Defects detection, Process Variation Measurement, Hardware-to-Models correlation, PUF, etc... Personal Website
Jim Aarestad is pursuing a Ph.D. in Engineering, majoring in Computer Engineering with a concentration on Computer Architecture. He earned a Bachelor's Degree in Computer Engineering from the University of New Mexico in 2009, and a Master's Degree in Computer Engineering, also from UNM, in 2011.
Jim is conducting research on physical unclonable functions (PUFs), including a PUF design based upon the REBEL on-chip path delay measurement macro. Research activities involve design and development of a complete technology demonstration system, including the PUF and an engine implementation for driving the PUF generation process. Additional research includes the application of advanced statistical metrics to characterize and compare PUF performance and the incorporation of error correction techniques for reliability enhancement of PUF-generated data. Personal Website
Jing Ju is pursuing her Ph.D. in Electrical Engineering majoring in Microelectronics. She has a Bachelor's and Master's degree with the major of Information and Communication Engineering from Hunan University in China.
Her research mainly focus on Physical Unclonable Functions based on Power Grid (PG-PUFs), which leverage the naturally occurring manufacturing variations within the power grid for each IC to produce repeatedly random digital identifiers. Currently, she is working on exploiting new architectures for PG-PUFs in order to improve the quality of bit streams generated from PUFs circuits.
Mitch Martin is pursuing his PhD in Computer Engineering majoring in Computer Architecture. He has a Bachelors and Masters degree from University of New Mexico in Computer Engineering.
His research focus is creating a new Physical Uncloneable Functions (PUF) for hardware authentication.
Currently he is working on the creation of new, improved and stable Physical Uncloneable Functions(PUFs).
Raj Chakraborty is pursuing his PhD in Electrical Engineering majoring in Micro Electronics. He has a Masters degree from University of .....
His research focus is on development of an on-chip system for using physical unclonable funtions for identification and secret key generation.
Raj is working with Intel since 200_ as a ...
William Cavanaugh is currently pursuing a Master's degree in Electrical Engineering with the specialization in Micro Electronics.
His research goal is to develop an on-line automatic test pattern generation algorithm for the purpose of reverse engineering and determining the functionality and netlist connectivity of an unknown IC.
Tony Mao is pursuing his Masters in Computer Engineering majoring in Computer Architecture.
Her research focus is on FPGA Dynamic Reconfiguration.
Carlos Montoya is pursuing his Masters in Computer Engineering majoring in Computer Architecture.
His Research focus is on Dynamic Partial Reconfiguration on FPGAs.
Currently he is working on extending the inherent flexibility of the FPGAs, Dynamic Partial Reconfiguration, that allows specific regions of the FPGA to be reprogrammed with new functionality while applications continue to run in the remainder of the device, for different applications. He will be demonstrating the Dynamic Partial Reconfiguration design flow using the newer Xilinx ISE 13 solution on a Virtex-5 ML506 Evaluation Platform.
Joshua Trujillo is pursuing his PhD in Computer Engineering majoring in Computer Architecture.
Currently he is working on researching high-speed PCB design. He is primarily focused on designs for FPGA chips.
Matt Areno is pursuing his PhD in Computer Engineering majoring in Computer Architecture. He has a Masters degree in Computer Engineering and Bachelors Degree in Electrical Engineering from Utah State University.
His research is on secure execution on mobile devices. He is looking at using integrated hardware security elements, such as ARM TrustZone technology, to provide a secure platform for application execution. His research will look into the possible incorporation of this technology on Apple iOS and Google Android based devices.
Aindrik Dutta is pursuing his PhD in Computer Engineering majoring in Computer Architecture. He has a Bachelor of Technology degree from West Bengal University of Technology majoring in Computer Science and Engineering.
He intend to direct his research towards exploiting hardware software dualities and design systems using hardware software co-design methodologies.
Fareena Saqib is pursuing her PhD in Computer Engineering majoring in Computer Architecture. She has a Masters degree in Computer Networks from University of New Mexico.
Her research focus is on using FPGAs for Hardware/Software Co-design acceleration.