Jim Plusquellic
Associate Professor, Department of
CSEE,
UMBC
CMPE 646: VLSI Design Verification and Test
Course Syllabus (PDF)
Introduction (PDF)
Overview (PDF)
Economics (PDF)
Defects (PDF)
Faults I (PDF)
Faults II (PDF)
Delay Faults I (PDF)
Delay Faults II (PDF)
Combinational ATPG I (PDF)
Combinational ATPG II (PDF)
Testability Measures (PDF)
Simulation (PDF)
Fault Simulation (PDF)
DFT Scan (PDF)
BIST I (PDF)
BIST II (PDF)
Announcements:
(8/28/07): Class will be held in IT/E 210.
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(10/8/07): Class is cancelled Oct. 22 and Oct. 24.
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(10/29/07): Midterm exam is scheduled for Oct. 31.
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Sample midterm exam
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Sample final exam
Homework:
Assignment #1, Due Sept. 26th (PDF)
Read and write a brief summary (< 3 paragraphs) on one algorithm discussed in each of the areas on test, physical design, logic synthesis and formal verification. (Assignment #2, Due Oct. 4th)
Read documentation on Encounter Test (ET).
cdsdoc initialization file
Cadence cshrc.cadence file -- type 'source cshrc.cadence' on cadence.gl.umbc.edu
ET start-up file.
ET start-up file.
Please download the cshrc.cadence file above (formerly cshrc.stdcadence) and source it if you are logged onto
cadence.gl.umbc.edu or cadence2.gl.umbc.edu to read the documentation (cdsdoc). It appears that 'et' will not run on
either of these machines and you will need to run et from the machines in ite375. I'll request access for
you guys for that room. You'll do the same thing, e.g., source the cshrc.cadence file when you log on to a
machine in ite375 but you'll first have to copy it to cshrc_nc.cadence, delete the 'if stmt' at the top of
the file -> if ( "$HOSTNAME" =~ cadence* || "$HOSTNAME" =~ don.cs.umbc.edu) then) and the last 'endif' at
the bottom of the file. Once you source cshrc_nc.cadence, you should be able to run et.
Please look through the documentation for CADENCE ET. Tutorial files including a design and library are located
at /afs/umbc.edu/software/cadence/software_2005/ET31/linux/tools.lnx86/tb/tutorials/dlx
Project:
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The site "http://www.fm.vslib.cz/~kes/asic/iscas/" gives the benchmark circuits that I discussed in
class. The ISCAS'85 circuits are given at the top of the first table. In particular, I want you to
run the c432 through the et tools, i.e., generate stuck patterns and reports. This is the first part
of the project due 11/28/04.
Cadence Links
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