ECE 337: Computer Architecture and Organization

Instructor: Jim Plusquellic
Department of ECE, UNM

* Course Syllabus

* Computer Systems Organization
* Digital Logic (Start from slide 33)
Mid-term includes the above slide sets + VHDL slides below.
* Instruction Set Architectures
* OS Essentials
* Intel Instruction Set Architecture
* Intel Architecture: Segmentation
* Intel Architecture: Paging
* DLX Architecture and Pipelining
* DLX Pipeline Hazards
* DLX Pipeline Hazards II

Text Slides:

* Introduction
* MicroArchitecture

Laboratory Lectures:

* VHDL Overview
* VHDL Basics
* Concurrent Signal Assignment
* Sequential Statements
* Sequential Design: Principles (Only components discussed in class)
* Material drawn from an excellent text book on VHDL:
RTL Harware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Pong P. Chu, ISBN-13: 978-0-471-72092-8 ISBN-10: 0-471-72092-5


* SAMPLE FINAL EXAM (COMPLETED: 12/7/2011 at 9:45am)
* Sorry for the delay in getting back to some of you -- my internet connection at home was down for most of the day.
Given we missed our review session today and teaching evals, I will post a review exam by tomorrow evening. At least some of the questions on the review exam WILL be on the final, so it is in your best interest to study it carefully and thoroughly.
I also need to ask you to do the teaching evals after the final on Wed. I will have a student outside the classroom who will hand you a teaching eval form and ask you to fill it out at the table in the atrium. I would very much appreciate you taking a couple minutes to fill it out -- especially valuable will be any comments you can provide as I intend to push changes through in our curriculum if I can.
SEE YOU WED for the final!
* !!!!!!!!!!!!!!!!!!!!!!! CLASS IS CANCELLED, WED. Nov 23rd !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* !!!!!!!!!!!!!!!!!!!!!!! CLASS IS CANCELLED, Mon. Nov 7th !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* I will allow some time for you to ask questions about the mid-term exam on Mon., Oct 17th.
* Sample Exam from ANOTHER CLASS (NOT THIS ONE). Since this is the first time I'm teaching this course, this is the best I can do.
* I will be distributing DVDs with Xilinx 12.4 and FPGA boards (,400,789&Prod=NEXYS2) sometime over the next 2 weeks.

Laboratory Notes:

* Spartan3E specs
* Please note that you will NOT be able to use the Xilinx programming tool with the USB cable and driver you are using, namely the Digitent Adept driver. You MUST use the Adept software instead (also on the DVD you have). Run it and select the bitfile to download to the FPGA. The Adept driver provides power to the Nexys2 board (so you don't need a power adapter), but in doing so, it disables the Xilinx programming tools, e.g., Impact driver for programming.
* Chip specs for ISE
* Nexys 2 website: Documentation, Master UCF file for the Nexys2-1200, etc.


* Lab 1: (due Oct. 10th, 2011)
* Lab 2: (due Oct. 24th, 2011)
* Lab 2 FILES
* Lab 3: (due Nov. 2nd, 2011)
* Lab 3 FILES
* Lab 4: (due Nov. 30th, 2011)
Jim Plusquellic / ECE /