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Jim Plusquellic

Associate Professor, Department of CSEE, UMBC

TAs

Ryan Helinski (Office hours: Monday 10am-12pm, ITE 353)(rhelins1@umbc.edu)

CMPE 415: Programmable Logic Devices

* Course Syllabus

* Introduction
* Introduction to Verilog
* Overview of Verilog
* FPGA Architectures I
* Verilog Data Types and Operators
* Verilog Event Driven Simulation
* Verilog Behavioral Constructs
* Verilog State Machines
* FPGA Architectures II
* Verilog Design Examples
* FPGA Architectures III
* Configuring an FPGA
* FPGA versus ASIC Design Styles
* Schematic-Based Design Flows
* HDL-Based Design Flows
* Silicon Virtual Prototyping

* Behavioral Synthesis Examples

Announcements:

* Required text for the class:
The Design Warrior's Guide to FPGAs, Devices, Tools and Flows, Clive "Max" Maxfield, ISBN: 0-7506-7604-3
Supplimentary texts include:
Advanced Digital Logic Design Using Verilog, State Machines and Synthesis for FPGAs, Sunggu Lee, ISBN: 0-534-55161-0
Modeling, Synthesis and Rapid Prototyping with the Verilog HDL, Michael D. Ciletti, ISBN: 0-13-977398-3
* "Architecture of FPGAs and CPLDs: A Tutorial", Stephen Brown and Jonathan Rose, Department of Electrical and Computer Engineering, University of Toronto (http://www.eecg.utoronto.ca/~jayar/pubs/brown/survey.pdf)
* Stephen Brown and Jonathan Rose, "Architecture of FPGAs and CPLDs: A Tutorial," IEEE Design and Test of Computers, Vol. 13, No. 2, pp. 42-57, 1996.
* "Learning the Ropes: FPGAs and CPLDs", Ingo Cyliax
* Other links
* 9/13/07: Please plan to meet in IT/E 210 today at 4pm for a tutorial on the Xilinx software. Since there are fewer computers than students, some of you will need to pick a partner to share a terminal with.
* 9/20/07: Please plan to meet in IT/E 210 today at 4pm for a tutorial on the XESS demo boards. Since there are fewer computers than students, some of you will need to pick a partner to share a terminal with.
* 9/27/07: Please plan to meet in IT/E 210 today at 4pm for a hardware demo and a lecture.
* 10/4/07: Please plan to meet in IT/E 210 today at 4pm for a tutorial on labview.
* 10/8/07: Class is cancelled Oct. 23 and Oct. 25.
* 10/8/07: Midterm is scheduled for Oct. 30th.
* Sample midterm exam
* 10/18/07: Please plan to meet in IT/E 210 today at 4pm for the second tutorial on labview.
* 11/8/07: Please plan to meet in IT/E 210 today for LAB #3 demos.
* 11/15/07: Please plan to meet in IT/E 210 today for LAB #4 demos and project discussion.
* STUDENT ABET SURVEY: Please complete before the last day of classes (Dec. 11th). Please take care to select the correct course when you login using your UMBC username/passwd.
* Kyle has my LABVIEW CD. Please return after you get LABVIEW installed. Thanks.
* I've asked Jane to give you weekend access.
* Class will be held in CMPE 210 both Thurs, Dec. 6th and Tues, Dec. 11th. On thursday, I'll will grade the projects for a max of 10 points on whether you are making progress on the project. Progress means having the LABVIEW part completed and at least some attempt to get the hardware to work. For example, you may want to use a small input file (say 2 or 4 values), transfer the data to the FPGA, compute the sine and cosine of the values and return them to LABVIEW for inspection. That would certainly constitute progress. The remaining 90 points will be used to grade the final project including the demo.
* IMPORTANT REMINDER: STUDENT ABET SURVEY: Please complete before the last day of classes (Dec. 11th). THIS SURVEY IS VERY IMPORTANT PART OF THE COURSE: I WILL LOOK TO SEE WHO HAS FILLED IT OUT BEFORE FINALIZING THE CLASS PARTICIPATION COMPONENT OF THE COURSE GRADE.
* Sample final exam

Laboratory Notes:

* FPGA boards contain the Xilinx Spartian II XC2S200 FPGA in a FG256 package. The FPGA supports 200,000 gates and 176 programmable I/Os.
* SPARTIAN XC2S200 product datasheet
* XSA Manual V1.3
* Laboratory demonstration source for Sept. 20th.
Verilog code for led display
User constraint file for led display lab
* FSM: 2-bit sequence detector (verilog file)
* FSM: 2-bit sequence detector (test bench)
* Six hour LABVIEW tutorial (PDF)
* Six hour LABVIEW tutorial (PPT)
* Six hour LABVIEW exercises (DOC)
* Six hour LABVIEW VIs (VIs)
* Lession 1-4 LABVIEW course tutorial (PPT)
* Lession 5-8 LABVIEW course tutorial (PPT)
* Lession 9-11 LABVIEW course tutorial (PPT)
*

Laboratories:

* LAB #0: (Assigned Sept 13, Due: Sept 20th.) Re-do the quick start tutorial, taking time to explore other options, particularly those associated with the test bench creation and simulation processes. I strongly encourage you to consider this request seriously and take advantage of this opportunity. The next tutorial that I will deliver will involve the use of the FPGA boards, and I will assume you are familiar with the flow that we talked about today.
* LAB #1 (Assigned Sept 20, Due: Sept 27th)
User constraint file for Lab #1
* LAB #2 (Assigned Oct 5, Due: Oct 16th)
WriteParallelPort.vi -- code that we developed in the tutorial.
ReadParallelPort.vi -- code that we developed in the tutorial.
ParallelPortInOut.vi -- code that we developed in the tutorial (NOT NEEDED FOR LAB #3).
Parallel port timing diagram
Parallel port template
Parallel port test bench
* LAB #3 (Assigned: Oct 19, Due: Thurs, Nov 8th)
Working state machine from LAB #2
Parallel port User Constraints File: YOU MUST USE THIS FILE! IT HAS BEEN UPDATED SO BE SURE TO DOWNLOAD IT AGAIN!
Parallel port Synthesis Constraints File: Add by right clicking on the SYNTHESIS flow symbol in ISE. Add this file to the constraints file item in the menu -- you'll click the file dialog widget on the right and add it by selecting this file. THIS FILE HAS ALSO BEEN UPDATED -- PLEASE DOWNLOAD AGAIN
WriteBitPP.vi -- code that we developed in the tutorial.
ReadBitPP.vi -- code that we developed in the tutorial.
My front panel for LAB #3
* LAB #4 (Assigned: Nov. 8th, Due: Nov 15th)
My timing diagram for LAB #4 (note it's multiple pages)
My test bench for LAB #4

Project:

* Final project description (ASSIGNED: 11/14/07, DUE: /12/11/07 & 12/11/07)(UPDATED: 11/19/07)(UPDATED:11/20/07)(UPDATED: 11/21/07)(SMALL UPDATE: 11/28/07)
* Example time domain triangle waveform
* Ryan's test bench for debugging the project
* Ryan's data file for debugging the project
* K.J. has pointed out that you will need to explicity declare your wires as signed in verilog, i.e., 'wire signed variable' since the default is unsigned.
* Some of you were not able to get your lab #4 to work properly. In order to give you a fighting chance on the project, I'm providing a link to my code below. NOTE: I have not tested this with the expanded memory 10 bit address space, so I'm not making any guarantees on whether this works as is. I would definitely try transferring 512 words back and forth between LABVIEW and the FPGA because modifying it for the project.
* My verilog code for LAB #4
* My LABVIEW code for LAB #4
* I completed the project recently -- it took me about 24 hours from start to finish. I discovered a few problems with the specification, which probably explains why those who had it working didn't get the correct results. The first problem deals with overflow. The scaling of the y float values to 16-bit integers caused overflow (I suspected this but now have confirmed it). My code started working at 12-bit integers but worse case analysis indicates that 9-bits is max -- I'm recommending 8-bits (see the proj desc for an update if you're interested). The second problem delt with the conversion of the real and imag back to floating point values. I indicated that you needed to add the 'zero' in the formula. This is only true for the DC component -- you add nothing to the other components. I've computed the mag and phase values of the 512 point triangle wfm using the FPGA and have given the results below.
* FPGA generated magnitude of example time domain triangle waveform
* FPGA generated phase of example time domain triangle waveform
Jim Plusquellic / CSEE / plusquel@umbc.edu