Associate Professor, Department of
CMPE 650: Digital Systems Design
Capacitance and Inductance
Power, Speed and Packages I
Power, Speed and Packages II
Scope Measurement Methods
Transmission Lines I
Transmission Lines II
Transmission Lines III
Transmission Lines IV
Transmission Lines V (revised, 3/12)
Transmission Lines VI (revised, 3/17)
Transmission Lines VII (revised, 3/18)
Transmission Lines VIII (revised, 3/28)
PCB Layer Stacks
Power Systems I
Power Systems II
Clock Distributions I
Clock Distributions II
Basic Circuit Theory Review I
This course is scheduled to meet in IT/E 241. Instead, let's meet in IT/E 210 for the lectures.
This course includes a laboratory that will meet from 3:00-4:00pm on Fridays in ITE 242.
Sample mid term exam
Sample final exam
I will give a LABVIEW lecture from 3:00-4:00pm this Fridays in ITE 242.
Unless I hear objections, let's move the lab from 3-4pm to 4-5pm on Fridays and plan to meet in
ITE 242 (NOT 210).
Burak found a nice tutorial on TTL circuits
A free SPICE simulator, courtesy of George.
Exam scheduled for March 25th. Includes topics up through and including transmission lines: RC mode (slide 12, transmission lines VI).
Details of laboratory grading criteria.
Six hour LABVIEW tutorial (PDF)
Six hour LABVIEW tutorial (PPT)
Six hour LABVIEW exercises (DOC)
Six hour LABVIEW VIs (VIs)
Lession 1-4 LABVIEW course tutorial (PPT)
Lession 5-8 LABVIEW course tutorial (PPT)
Lession 9-11 LABVIEW course tutorial (PPT)
Tektronics 3054B prog. manual (thanks to Jim :)
Tektronics AFG310 doc (thanks to Ryan Helinski)
Agilent E3631A doc (thanks to Ryan Helinski)
Ekarat's Capture CIS tutorial
Ekarat's Layout Plus tutorial
Cadence ORCAD documentation link
In order to work through the tutorial that Ekarat, you'll need footprints for the parts
identified in the tutorial. George has looked these up as:
8086MIN -> DIP.100/40/W.600/L2.025
74LS373 -> DIP.100/20/W.300/L1.025
CON20 -> WALCON.100/RH/TM20E/W.550/20
The footprints of the components you will need for the lab are as follows:
RF/BNC/R1.350 (for BNC connectors)
SM/R_1206 (for resistors)
TP (for TEST_POINTs)
George's tutorial on event structures in LABVIEW
Shiva's tutorial on PCB board fabrication (work in progress so subject to revisions)
Part specs for Lab #3:
Dual D-type FF: http://focus.ti.com/docs/prod/folders/print/sn74hc74.html
Dual D-type FF
Hex Schmitt Trigger: http://www.fairchildsemi.com/pf/MM/MM74HC14.html
Hex Schmitt Trigger
Potentiometer: http://www.bourns.com/pdf/3296.pdf (Courtesy of George)
SMA edge mount, 50 Ohms: http://www.molex.com/cgi-bin/bv/molex/jsp/products/datasheet.jsp?part=active/0732511150_RF_COAX_CONNECTORS.xml&BV_SessionID=@@@@1064233079.1206726637@@@@&BV_EngineID=ccccadedjfleiddcflgcehedffgdfmk.0&channel=Products&Lang=english
Can't get George's LAB3.LLB to merge so you'll need to create a footprint or find a comparible
footprint on your own
Here is the Digi-Key order that I placed, which includes capacitors, resistors, etc.
Some (most) of you have had trouble with the etching part. Please be sure to warm up the solution
with the heater before performing the etch. Unlike feric chloride, the Ammonium Persulfate is
temperature sensitive. Be careful with the heater -- it must be tipped over to keep the majority
of the glass portion under solution, but you must NOT submerge the rubber control area on the top
so be careful.
The lab board fabrication area is getting messy. Please clean up the area after you finish you board
fabrication. I'm asking Shiva to let me know who was the last person to fabricate their board, so
if it's a mess when I stop by, expect to hear from me.
As an exercise, simulate the TTL inverter and ECL output driver discussed in class using
SPICE, Pspice or Spectra. Use rise/fall times of 1 ns. Print waveforms for the output and
power supply current.
You'll need to look up typical values for the resistors shown in the slide sets.
I found a PSPICE BJT model (NPN) at:
We also have some spectra models under cadence:
In particular, 'rfModels.scs' has several NPN and PNP models you can use in a Spectra simulation.
Found one spice model at http://www.zetex.com/3.0/3-10.asp
And one hspice model at http://www.ece.uci.edu/docs/hspice/hspice_2001_2-110.html
George pointed me to Analog Devices, SPICE model under 'Matched Transistors' at:
Lab 1: Assigned Feb 8, Due Feb 15.
LAB 1 demos. Work through tutorials for capture CIS and layout plus.
Lab 2: Assigned Feb 22, Due March 7 and March 14.
Lab 2: Locations to set your datums to (courtesy of George)
Lab 3: Assigned March 24, Due March 28 and April 4 (ext. to April 11)(UPDATED with Part numbers: 3/28)
Jim Plusquellic /
Preliminary project description: Assigned April 8th, Due May 9th