ECE 338: Intermediate Logic Design

Lectures and Screen Casts

VHDL Essentials I
VHDL Essentials I(A) (video)
VHDL Essentials I(B) (video)
VHDL Essentials I(C) (video)
VHDL Essentials II
VHDL Essentials II(A) (video)
VHDL Essentials II(B) (video)
VHDL Essentials III
VHDL Essentials III(A) (video)
VHDL Essentials III(B) (video)
VHDL Essentials III(C) (video)
VHDL Essentials IV
VHDL Essentials IV(A) (video)
VHDL Essentials IV(B) (video)
VHDL Essentials IV(C) (video)
VHDL Essentials IV(D) (video)
VHDL Essentials V
VHDL Essentials V(A) (video)
VHDL Essentials V(B) (video)
VHDL Essentials V(C) (video)
VHDL Essentials V(D) (video)

Supplemental Lecture Material

Course Introduction
VHDL Overview
VHDL Essentials
Concurrent Signal Assignment
Sequential Statements
VHDL Synthesis
Combinational Design
Sequential Design: Principles
Sequential Design: Practice
Finite State Machines
RTL: Principles
RTL: Practice

Supplementary Laboratory Material:

Announcements:

Sample Final Exam

Links:

Prof. Pong Chu's slides

Digilent Zybo page + tutorials

Zynq SoC Overview

Block diagrams from Zynq SoC Overview

Laboratory Notes: ZYBO:

Some of you are using the ZYBO board you bought in my previous classes. Here are the corresponding links for ZYBO.

ZYBO Z7-10 Master XDC file

ZYBO Z7-10 Boot Files

ZYBO Z7-20 Boot Files

ZYBO Z7-10 Board Files (Add these files to (Xilinx_install_dir)/Vivado/2020.2/data/boards/board_files/zybo-z7-10/A.0/ directory)

Ivan Bow's tutorial on how to run linux on a Window's 10 machine

ZYBO Z7-07S Purchase, Vivado Installation, Board Files, BOOT Instructions

FPGA Architecture

LABORATORY GRADING CRITERIA

Laboratory Lectures:

Vivado: Installation, Part A (video)
Vivado: Installation, Part B (video)
Vivado: Create Project, Part A (video)
Vivado: Create Project, Part B (video)
Vivado: Synthesis, Part A (video)
Vivado: Synthesis, Part B (video)
Vivado: Program FPGA (video)
Vivado: Hardware Demo: Even Detector (video)

Vivado: SoC Programming Concepts (video)
Vivado: Block Diagram Tool, Part A (video)
Vivado: Block Diagram Tool, Part B (video)
Vivado: Adding Custom VHDL to the Block Diagram, Part A (video)
Vivado: Adding Custom VHDL to the Block Diagram, Part B (video)
Vivado: Adding Custom VHDL to the Block Diagram, Part C (video)
Vivado: SDK I(A), Create Application (video)
Vivado: SDK I(B), Create Application (video)
Zach Montoya and Andrew Rodriguez: Vitis and scp Ubuntu Instructions

Laboratories:

Please print out all lab reports and give them to me in class on the day they are due. DO NOT EMAIL THEM TO ME. I will NOT accept them through email.

Lab 0 Assignment: Create project, Synthesize, Program FPGA and carry out Hardware Demo using even detector

Lab 1 Assignment: Create project, Synthesize, Inspect schematic

Lab 2 Assignment: Create project, Synthesize, Inspect schematic, Compose your own VHDL

Lab 3 Assignment: Create project, Synthesize, Inspect schematic, Compose your own VHDL

Lab 4 Assignment: Create project, Synthesize, Inspect schematic, Compose your own VHDL

Lab 5 Assignment: Create project, Synthesize, Inspect schematic, Compose your own VHDL

Lab 6 Assignment: Implement a block diagram in Vivado

Lab 7 Assignment: Utilize the multiplier from a C program

Lab 8 Practice: Read/write to PL-side BRAM from a C program

Vivado project with HDMI driver and state machine for PS-PL GPIO (Vivado 2018.2)(HDMI driver courtesy of Charles Helmich): Note you must delete the user repository and re-add it, see Ben's video in announcements on canvas. Prepare live in-class demo

Pong Game: Vivado project with HDMI driver and state machine for PS-PL GPIO (Vivado 2018.2)(HDMI driver courtesy of Charles Helmich): : Note you must delete the user repository and re-add it, see Ben's video in announcements on canvas. Prepare live in-class demo

Ben's video on how to refresh the repo for the HDMI driver (NOTE: Be sure to set the jumper to QPSI, NOT SD card)

Simulation Example: BRAM

BRAM simulation project (tar.gz)

Project:

Everyone needs to pick a partner and decide on the game that they want to implement by Mon, Oct. 23rd. As specified in the project description, the Pong game will be provided as a template, and you can at a minimum just add features to Pong to pass the course. But you are encouraged to pick a completely different game, one that you will have fun coding in VHDL. I will provide you with the HDMI module that you will need to add to your block diagram next week so you can get Pong up and running. You are not allowed to leverage any VHDL that exists in public respositories (I have a list of links that I've maintained over the years that I check periodically). I will inspect your code as you develop it and it is relatively easy to distinguish student VHDL from public versions. Plus you will present features of your game live in class incrementally until the project demos are given at the end of the term, and I'll have the opportunity to watch you develop the game. I will also ask you at some point to update your code to make a change to a feature of your game as a mechanism to test your knowledge of your own code, so play it safe and write your own VHDL!

Project Description