ECE 338: Intermediate Logic Design

Instructor: Jim Plusquellic
Department of ECE, UNM

* Course Syllabus

Lectures and Screen Casts

* VHDL Essentials I
* VHDL Essentials I(A) (video)
* VHDL Essentials I(B) (video)
* VHDL Essentials I(C) (video)
* VHDL Essentials II
* VHDL Essentials II(A) (video)
* VHDL Essentials II(B) (video)
* VHDL Essentials III
* VHDL Essentials III(A) (video)
* VHDL Essentials III(B) (video)
* VHDL Essentials III(C) (video)
* VHDL Essentials IV
* VHDL Essentials IV(A) (video)
* VHDL Essentials IV(B) (video)
* VHDL Essentials IV(C) (video)
* VHDL Essentials IV(D) (video)
* VHDL Essentials V
* VHDL Essentials V(A) (video)
* VHDL Essentials V(B) (video)
* VHDL Essentials V(C) (video)
* VHDL Essentials V(D) (video)

Supplemental Lecture Material

* Course Introduction
* VHDL Overview
* VHDL Essentials
* Concurrent Signal Assignment
* Sequential Statements
* VHDL Synthesis
* Combinational Design
* Sequential Design: Principles
* Sequential Design: Practice
* Finite State Machines
* RTL: Principles
* RTL: Practice

Supplementary Laboratory Material:

* Xilinx generated schematics from lecture slides
* UART documentation and VHDL code
* VGA documentation and VHDL code
* Divider VHDL code


* Sample Final Exam


* Prof. Pong Chu's slides
* Digilent Zybo page + tutorials
* Zynq SoC Overview
* Block diagrams from Zynq SoC Overview

Xilinx Vivado documentation:

* Zynq Concepts, Tools, and Techniques on ZedBoard (2014.2) (read more link)
* Vivado Embedded system tutorial (2013.2)
* Vivado tutorial (2013.2)

Laboratory Notes:

* 8/21/2019: Please watch the Installation videos and in particular, create accounts on both the Digilent and Xilinx websites. After you've been approved as a student, you will be notified and will be able to buy the Zybo Z7 FPGA at the discount academic price. Be sure to buy the "Z7" version and not the older version (which was not Z7).
* ZYBO Z7-10 Boot Instructions
* ZYBO Z7-10 Master XDC file
* ZYBO Z7-10 Boot Files (NOTE: Linux_with_root_filesystem directory contains instructions on creating an SD card with a persistent root filesystem while Linux_with RAMDISK_filesystem are boot files for traditional RAMDISK filesystem (non-persistent) (Root filesystem images created courtsey of Ivan Bow).
* ZYBO Z7-20 Boot Files
* ZYBO Z7-10 Board Files (Add these files to (Xilinx_install_dir)/Vivado/2017.2/data/boards/board_files/zybo-z7-10/A.0/ directory)
* Ivan Bow's tutorial on how to run linux on a Window's 10 machine
* Network instructions

Laboratory Lectures:

* Vivado: Installation, Part A (video)
* Vivado: Installation, Part B (video)
* Vivado: Create Project, Part A (video)
* Vivado: Create Project, Part B (video)
* Vivado: Synthesis, Part A (video)
* Vivado: Synthesis, Part B (video)
* Vivado: Program FPGA (video)
* Vivado: Hardware Demo: Even Detector (video)

* Vivado: SoC Programming Concepts (video)
* Vivado: Block Diagram Tool, Part A (video)
* Vivado: Block Diagram Tool, Part B (video)
* Vivado: Adding Custom VHDL to the Block Diagram, Part A (video)
* Vivado: Adding Custom VHDL to the Block Diagram, Part B (video)
* Vivado: Adding Custom VHDL to the Block Diagram, Part C (video)
* Vivado: SDK I(A), Create Application (video)
* Vivado: SDK I(B), Create Application (video)


* Please print out all lab reports and give them to me in class on the day they are due. DO NOT EMAIL THEM TO ME. I will NOT accept them through email.
* Lab 0: Files: Create project, Synthesize, Program FPGA and carry out Hardware Demo using even detector
* Lab 1 (PDF)
* Lab 2 (PDF)
* Lab 3 (PDF)
* Lab 4 files
* Lab 5 (PDF)
* Lab 6 files
* Lab 7 files
* Lab 8 README.txt
* Lab 8 files: Vivado projects for HDMI video driver, courtesy of Ivan and Charles
* Lab 8: Github site for HDMI video driver, courtesy of Charles
* Lab 9 (PDF)
* Lab 10 (PDF)


* Project Description (PDF)
* Project presentation can be given Wed. morning, Dec. 12th between 11am and 12pm (for 5 additional bonus points) or on Friday morning between 11 and 12.
Jim Plusquellic / ECE /