Assistant Professor, Department of
Teaching Assistant, ECS 208, MW 2:00-4:00, firstname.lastname@example.org
CMPE 413/CMSC 711: Principles of VLSI Design/VLSI Systems
Course Syllabus (PDF)
Basics (PDF) (mod:11/26)
Technology (PDF) (mod:11/26)
CMOS Processing Technology (Part I)(mod:11/26)
CMOS Processing Technology (Part I)(PDF) (mod:11/26)
CMOS Processing Technology (Part II)(mod:11/26)
CMOS Processing Technology (Part II)(PDF) (mod:11/26)
Details of the MOS transistor (mod:11/26)
Details of the MOS transistor (PDF) (mod:11/26)
Circuit and System Representations (mod:11/26)
Circuit and System Representations (PDF) (mod:11/26)
END MATERIAL EXAM I
Performance Estimation (Part I)(mod:11/26)
Performance Estimation (Part I) (PDF) (mod:11/26)
Performance Estimation (Part II) (mod:11/26)
Performance Estimation (Part II) (PDF) (mod:11/26)
CMOS Circuit and Logic Design (Part I) (mod:11/26)
CMOS Circuit and Logic Design (Part I) (PDF) (mod:11/26)
CMOS Circuit and Logic Design (Part II) (mod:11/26)
CMOS Circuit and Logic Design (Part II) (PDF) (mod:11/26)
END MATERIAL EXAM II
Subsystem Design (Part I) (mod:11/26)
Subsystem Design (Part I) (PDF) (mod:12/4)
Subsystem Design (Part II) (mod:11/20)
Subsystem Design (Part II) (PDF) (mod:11/20)
Subsystem Design (Part III) (mod:11/20)
Subsystem Design (Part III) (PDF) (mod:11/20)
Transistor Level Implementation of CMOS Combinational Logic Circuits, Jeff Beasley and William Hudson
"Taking Moore's Law Into the Next Century" by Scott Hamilton, Computer, Jan 1999 (PDF)
1999 Introduction to ITRS (PDF)
(9/1): Meeting time MW 4:00-5:15. Classroom MP 010. This is a 4 credit class. Laboratory is set
for Friday at 2:00-4:00 BUT MAY CHANGE. Stay tuned to these announcements. Laboratory attendance
(9/8): Laboratory meeting time is changed to Friday at 1:00-3:00 !
(9/8): AMI 1.6um technology in Cadence is working now.
(9/29): Please use the AMI 0.6um technology now since you will be fabricating
this term in this technology.
(10/20): NOTE: THE FIRST EXAM IS SCHEDULED FOR OCT. 25th (not the 23rd as indicated on the syllabus).
(10/24): EXAM 1: You MUST bring a calculator to class for the exam. The exam is closed notes and closed book. Concepts from labs 1 through 4 are fair game.
(11/19): EXAM 2: You MUST bring a calculator to class for the exam. The exam is closed notes and closed book. Concepts from labs 5 and 6 are fair game. The exam is NOT cummulative -- it covers Chapters 4 and 5 ONLY ! Please be sure to print out the latest lecture slides from my web site. The slides from Chapter 5 will be available tomorrow afternoon.
(11/19): Virtuoso and Composer are working again. I've also unpacked the IEEE stuff under ldv -- which should fix the 'std_logic' errors you are getting. Let me know if this is not true. Don't forget to choose AMI 0.6 C5N as the technology.
(11/20): EXAM 2: THE SECOND EXAM IS SCHEDULED FOR NOV. 27th (not the 22nd as indicated on the syllabus).
(11/20): NOTE: The fix to ncvhdl to get rid of the 'std_logic' error is to include the following line in your cds.lib: DEFINE synopsys /cds/ldv/tools/inca/files/SYNOPSYS. I've included this line in the cds.lib file reference below under Cadence.
(12/11): FINAL EXAM: THE FINAL EXAM IS SCHEDULED FOR DEC. 18th at 3:30pm in the same
room (MP 010). The exam is cummulative: 1/2 on lecture slides 8.1 and 8.2 and 1/2 on the material
covered on the first two exams. You MUST bring a calculator to the exam! You will have 2 hours --
the final will be approximately the same length as the regular exams.
(12/11): There is NO class on Wed, 12/13! Please use this time to work on your projects and
study for the final.
Sample Exam I
Sample Exam II
Sample Exam III
Sample Exam IV (PDF)
Sample Exam V (PDF)
Project description (12/12/2000) (pdf) (THIS IS THE LATEST -- includes a PAD FRAME specification).
Due on Nov. 10th: Descriptions of the Adder and Multiplier you are going to design.
Due on Dec. 8th: VHDL and simulation results for the Adder and Multiplier, as well
as Composer schematics.
(12/11): The final project report is due on Dec 19th -- the day after the final!
(12/12) Your core logic MUST be placed and wired up to this
pad frame (which you need to import into Cadence as a cif file).
The I/O pads are arranged as given in the project description. Some groups are
doing special projects. In these cases, please feel free to rearrange the I/O
cells. You can NOT add pads or redefine the I/O pad frame perimeter.
To import, simply bring up the import option under icfb and choose CIF...
Specify the above file as the Input File and FRAME4B as the Top Cell Name.
Add a Library name of your choice and click OK. The cell name is frame4b.
You should have a layout view for it. (NOTE: I imported this for a couple groups
yesterday -- those groups should reimport the FRAME4B using this latest version
Layout slides showing design rules graphically (ps)
Layout slides showing design rules graphically (pdf)
Actual SCMOS design rules in text (ps)
Actual SCMOS design rules in text (pdf)
An example showing how to build n-substrate contacts (n-well plugs)(pdf)
CMOS Circuit and Logic Design (Part I) (mod:9/15)
CMOS Circuit and Logic Design (Part I) (PDF) (mod:9/15)
Go to http://winfiles.cnet.com/apps/98/terminals.html to get X-Win32 to run Cadence under Windows (according to Ryan Robucci).
Basic MOS models -- put them into the cadence/cell_design/models/ directory. You will have to create the models directory. (9/22)
New lines to ADD to your cds.lib file in cadence/cell_design/ directory. Preserve your existing contents. (9/22)
Please remove or change the 'setenv PRINTER cs1post' in the .cshrc file that I have
given you. Set it to cs2post or cs3post. Some of you are printing the CADENCE manuals to cs1post
(by accident, I think), which is not permitted (9/25).
Contrary to what I told you in lab today, I think I'll be able to keep Cadence working seamlessly
across the transition to the new version. At least, this is what the Cadence people have promised
me. In other words, there should be NO downtime -- which means you have a full two weeks to work
on this lab. (9/29)
Here is the 0.6um mos06.scs file you'll need to run simulations in the new technology. (10/9)
NOTE: DO NOT STACK VIAs or CONTACTS in your layouts. The DRC checker will NOT give you a design rule error -- but you will NOT be able to fabricate your design !(10/9)
NOTE: DO NOT SET any dimension in your LAYOUT OPTIONS dialog less than the value of lambda ! For example, do NOT use 0.15 in a 0.6um technology for any parameter -- the smallest value you can use is 0.3. (10/9)
Okay... Some of you have pointed out that the 0.6um MOS models were not available
until this past Monday which prevented you from making the simulation runs for
this week's lab. You can hand in lab #4 on Monday BEFORE class if you like. Note
that you WILL have a lab #5 due on Friday, Oct 20th.
The following 5 files are needed to complete the VHDL laboratory and tutorial. Please refer to the tutorial for explicit instructions on how to run the command line version. The GUI tutorial should be available next week.
The cds.lib file to install in the vhdl directory that you make. (10/20)
The hdl.var file to install in the vhdl directory that you make. (10/20)
The vhdl.vhd file for inverter -- install in inverter/vhdl directory (see tutorial). (10/20)
The vhdl.vhd file for inverter -- install in inverter_test/vhdl directory (see tutorial). (10/20)
In order to access the NCSU TDK, add the following to your .cshrc. See the tutorials under the Cadence link below. (NCSU ver 1.2) (11/23)
Here is my .cshrc in case you have trouble. (NCSU ver 1.2)
The .cshrc file to source for NC-VHDL and simulations, e.g. type 'source .cshrc.sim'. (NOTE: OUT-OF-DATE (NCSU ver 1.1): Probably don't need to do this anymore if you've used the latest .cshrc info given above) (10/20)
Laboratory I: Assigned Sept 8th, due Sept 15th.
Laboratory II: Assigned Sept 15th, due Sept 22th (PDF).
My laboratory II solutions (PDF).
Laboratory III: Assigned Sept 22th, due Sept 29th.
Laboratory IV: Assigned Sept 29th, due Oct 13th (PDF). Please do this assignment using AMI's C5N 0.6um process.
Laboratory V: Assigned Oct 13th, due Oct 20th.
Laboratory VI: Assigned Oct 20th, due Nov 3rd (PDF).
Cadence Tutorials (Courtesy Chintan Patel)
UMBC tutorial on Virtuoso (layout)(PDF)(10/16).
UMBC tutorial on NC-VHDL (VHDL)(PDF)(10/20).
Tutorial on how to synthesize schematics from VHDL that is compatible with LVS (11/26)
Tutorial on how to synthesize schematics from VHDL that is compatible with LVS (PDF) (11/26)
General Information about NCSU CDK. Be sure to read 'get started' and
'a Short FAQ'. 'a short paper on the CDK' is also useful.
NCSU Schematic Tutorials
Layout Examples (Magic versions):
NAND gate (PS)
2-input mux (PS)
XOR gate (PS)
My slides on VHDL
My slides on VHDL (PDF) (10/27)
VHDL Keywords (PDF)
Jim Plusquellic /
Linux CAD Software