Date |
Day |
Topic |
Reading/Coverage |
August 17
|
Mon |
Introduction to Digital Electronics |
Handout |
August 19
|
Wed |
Basic Circuits with Diodes |
1.1
- 1.8 |
August 24
|
Mon |
Basic Solid State Physics |
2.1 - 2.3 |
August 26
|
Wed |
Physics of Semiconductor Diodes |
2.4 - 2.6 |
August 31
|
Mon |
Physics of Semiconductor MOSFETs
|
3.1 |
September 02
|
Wed |
MOSFET I-V Characteristics |
3.2 |
September 07
|
Mon |
Labor
Day |
- |
September 9 |
Wed |
Basic Circuits with MOSFET |
Handout
|
September 14
|
Mon |
MOSFET Threshold Voltage & Parasitic
Capacitance |
Handout |
September 16
|
Wed |
PSPICE Review
|
-
|
September 21
|
Mon |
MOSFET Scaling Issues |
Handout
|
September 23 |
Wed |
Basic Digital Circuits with MOSFETs |
Handout
|
September 28
|
Mon |
CMOS Inverter VTC & ITC
|
5.1
- 5.4 |
September 30
|
Wed |
CMOS Inverter Noise Margin & Delay
Model
|
5.5 |
October 05
|
Mon |
CMOS Inverter Power
|
5.6
|
October 07
|
Wed |
TEST |
- |
October 12
|
Mon |
CMOS Inverter Short Circuit Power |
5.6 |
October 14
|
Wed |
CMOS Inverter Leakage Power |
5.7 |
October 19
|
Mon |
Gate Sizing (Inverter Chain)
|
5.8 |
October 21
|
Wed |
Interconnect Modeling I |
4.1
- 4.2 |
October 26
|
Mon |
Interconnect Modeling II |
4.3 - 4.4 |
October 28
|
Wed |
CMOS Fabrication |
12.1 - 12.9 |
November 02 |
Mon |
Design Rules & Basic Layout Techniques
|
11.1
- 11.6
|
November 04
|
Wed |
TEST |
- |
November 09 |
Mon |
Combinational Logic: NAND & NOR
Gates |
6.1
- 6.2 |
November 11 |
Wed |
Combinational Logic: Transmission
Gates |
6.3 |
November 16
|
Mon |
Logic Design Style: Static Logic |
7.1
|
November 18
|
Wed |
Logic Design Style:
Dynamic & Damino Logics
|
7.2 - 7.3
|
November 23 |
Mon |
Sequential Logic: D Flip-Flop |
8.1 - 8.4 |
November 25
|
Wed |
Timing Analysis |
8.9 |
November 30 |
Mon |
SRAM Memories |
9.1
- 9.3 |
December 02 |
Wed |
DRAM & FLASH Memories |
9.4
- 9.6 |
December 07
|
Mon |
Final
Exam (5:30-7:30PM) |
- |