Acknowledgments:

Publications 2001-2005: supported by Faculty Partnership Awards from IBM's Austin Center for Advanced Studies (ACAS) Program.
Publications 2001-2004: supported by an NSF grant, award number 0098300 and by Intel Corp. through computing equipment donations.
Publications 2007-2010: supported by an NSF grant, award number 0852949.
Publications 2010-2015: supported by an NSF grants, award numbers 1018748 and 1118025.
Publications 2015-2018: supported by companies and investors.
Publications 2019-2021: supported by companies and NSF grant, award number 1813945.

2019:

    * J. Calhoun, C. Minwalla, C. Helmich, F. Saqib, W. Che, J. Plusquellic, Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash)", MDPI, 2019.

    * A. S. Siddiqui, G. Shirley, S. Bendre, G. Bhagwat, J. Plusquellic, F. Saqib, Secure Design Flow of FPGA Based RISC-V Implementation", IVSW, 2019

    * D. Forte, S. Bhunia, R. Karri, J. Plusquellic, M. Tehranipoor, IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present and Future", ITC, 2019

2018:

    * A. Siddiqui, Y. Gui, D. Lawrence, S. Laval, J. Plusquellic, M. Manjrekar, B. Chowdhury, F. Saqib, Hardware Assisted Security Architecture for Smart Grid, IECON, 2018.

    * J. Plusquellic and M. Areno, Correlation-Based Robust Authentication (Cobra) using Helper Data Only, Cryptography, MDPI, 2018.

    * D. Owen Jr., D. Heeger, C. Chan, W. Che, F. Saqib, M. Areno and J. Plusquellic, An Autonomous, Self-Authenticating and Self-Contained Secure Boot Process for FPGAs, Cryptography, MDPI, 2018.

    * G. Pocklassery, W. Che, F. Saqib, M. Areno and J. Plusquellic, Self-Authenticating Secure Boot for FPGAs, Hardware-Oriented Security and Trust, 2018.

    * W. Che, M. Martinez-Ramon, F. Saqib and J. Plusquellic, Delay Model and Machine Learning Exploration of a Hardware-Embedded Delay PUF, Hardware-Oriented Security and Trust, 2018.

2017:

    * W. Che, F. Saqib and J. Plusquellic, Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF, Trans. on VLSI, 2017.

    * A. S. Siddiqui, C.-C. Lee, W. Che, J. Plusquellic and F. Saqib, Secure Intra-Vehicular Communication over CANFD, AsianHOST, 2017.

    * W. Che, V. K. Kajuluri, F. Saqib and J. Plusquellic, Leveraging Distributions in Physical Unclonable Functions, Cryptography, MDPI, 2017.

    * W. Che, V. K. Kajuluri, M. Martin, F. Saqib* and J. Plusquellic, Analysis of Entropy in a Hardware-Embedded Delay PUF, Cryptography, MDPI, 2017.

    * G. Pocklassery, V. K Kajuruli and F. Saqib, J. Plusquellic, Physical Unclonable Functions and Dynamic Partial Reconfiguration for Security in Resource-Constrained Embedded Systems, Symposium on Hardware-Oriented Security and Trust (HOST), 2017.

    * A. S. Siddiqui, Y. Gui, J. Plusquellic and F. Saqib, Secure Communication over CANBus, International Midwest Symposium on Circuits and Systems (MWSCAS), 2017.

    * A. S. Siddiqui, Y. Gui, J. Plusquellic and F. Saqib, A Secure Communication Framework for ECUs, Advances in Science, Technology and Engineering Systems Journal, Special issue on Recent Advances in Engineering Systems, 2017, pp. 1307-1313.

2016:

    * W. Che, M. Martin, G. Pocklassery, V. K. Kajuluri, F. Saqib and J. Plusquellic, A Privacy-Preserving, Mutual PUF-Based Authentication Protocol, Cryptography, Vol. 1, Issue 1, 2016.

    * D. Ismari, C. Lamech, Swarup Bhunia, F. Saqib, and J. Plusquellic, On Detecting Delay Anomalies Introduced by Hardware Trojans, International Conference on Computer-Aided Design, 2016.

    * F. Zhang, S. Bhunia, J. Plusquellic, Current based PUF Exploiting Random Variations in SRAM Cells, Design and Automation in Europe (DATE), 2016.

2015:

    * W. Che, F. Saqib, and J. Plusquellic, PUF-Based Authentication, INVITED PAPER, ICCAD, Nov, 2015.

    * I. Wilcox, F. Saqib, and J. Plusquellic, GDS-II Trojan detection using Multiple Supply Pad VDD and GND IDDQs in ASIC Functional Units, HOST, 2015.

    * C. Konstantinou, M. Maniatakos, F. Saqib, Shiyan Hu, J. Plusquellic, Yier Jin, Cyber-Physical Systems: A Security Perspective, ETS, May, 2015.

2014:

    * F. Saqib, D. Ismari, C. Lamech and J. Plusquellic, Within-Die Delay Variation Measurement and Analysis Using An Embedded Test Structure, Trans. on VLSI, Vol. PP, Issue 99, May, 2014.

    * D. Ismari and J. Plusquellic, IP-Level Implementation of a Resistance-Based Physical Unclonable Function, Symposium on Hardware-Oriented Security and Trust (HOST), 2014, pp. 64-69.

    * W. Che, S. Bhunia and J. Plusquellic, A Non-Volatile Memory based Physically Unclonable Function without Helper Data, International Conference on Computer-Aided Design, 2014.

    * F. Saqib, M. Areno, J. Aarestad and J. Plusquellic, An ASIC Implementation of a Hardware-Embedded Physical Unclonable Function , IET Computers & Digital Techniques, Vol. 8, Issue 6, Nov. 2014, pp. 288-299.

2013:

    * J. Ju, R. Chakraborty, C. Lamech and J. Plusquellic, Stability Analysis of a Physical Unclonable Function based on Metal Resistance Variations, Symposium on Hardware-Oriented Security and Trust (HOST), 2013, pp. 143-150.

    * J. Aarestad, J. Plusquellic, D. Acharyya, Error-Tolerant Bit Generation Techniques for Use with a Hardware-Embedded Path Delay PUF, Symposium on Hardware-Oriented Security and Trust (HOST), 2013, pp. 151-158.

    * R. Chakraborty, C. Lamech, D. Acharyya and J. Plusquellic, A Transmission Gate Physical Unclonable Function and On-Chip Voltage- to-Digital Conversion Technique, Design Automation Conference (DAC), 2013, pp. 1-10.

    * J. Aarestad, P. Ortiz, D. Acharyya and J. Plusquellic, HELP: A Hardware-Embedded Delay-Based PUF, Design and Test of Computers, Mar., 2013, pp. 17-25.

    * M. Areno and J. Plusquellic, Secure Mobile Association and Data Protection with Enhanced Cryptographic Engines, International Conference on Privacy and Security in Mobile Systems (PRISMS), 2013.

    * M. Martin and J. Plusquellic, An On-Chip High Resolution Measurement Structure for Measuring Path Delays in an Arbiter PUF, Unpublished, 2013.

    NOTE: THE FOLLOWING THREE PAPERS HAVE BEEN 'DISCLOSED' ON MARCH 15th (PRIOR TO THE CHANGE IN PATENT LAW) and HAVE BEEN ACCEPTED FOR PUBLICATION:

    * J. Ju, C. Lamech, J. Plusquellic, Stability Analysis of a Physical Unclonable Function based on Metal Resistance Variations, Symposium on Hardware-Oriented Security and Trust (HOST), 2013.

    * J. Aarestad, D. Acharyya, J. Plusquellic, An Error-Tolerant Bit Generation Technique For Use With A Hardware-Embedded Path Delay PUF, Symposium on Hardware-Oriented Security and Trust (HOST), 2013.

    * R. Chakraborty, C. Lamech, D. Acharyya and J. Plusquellic, A Transmission Gate Physical Unclonable Function and On-Chip Voltage-to-Digital Conversion Technique, Design Automation Conference, 2013.

    * F. Saqib, A. Dutta, J. Plusquellic, P. Ortiz, M. S. Pattichis, Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF), IEEE Trans. on Computers, Volume: PP , Issue: 99, pp. 1, Oct. 2013.

    * M. Martin and J. Plusquellic, An On-Chip High Resolution Measurement Structure for Measuring Path Delays in an Arbiter PUF, Unpublished, 2013.

2012:

    * M. Abramovici, D. Agarwal, S. Bhunia, P. Bradley, M. S. Hsiao, J. Plusquellic and M. Tehranipoor, Protection against Hardware Trojan Attacks: Towards a Comprehensive Solution, Volume: PP , Issue: 99, Design and Test of Computers, 2012.

    * H. Salmani, M. Tehranipoor and J. Plusquellic, A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time, Transactions on VLSI, Volume: 20 , Issue: 1, 2012 , pp. 112-125.

    * M. Areno and J. Plusquellic, Securing Trusted Execution Environments with PUF Generated Secret Keys, TrustCom, 2012.

    * J. Ju, R. Chakraborty, R. Rad, J. Plusquellic, Bit String Analysis of Physical Unclonable Functions based on Resistance Variations in Metals and Transistors, Symposium on Hardware-Oriented Security and Trust (HOST), 2012, pp. 13-20.

    * C. Lamech and J. Plusquellic, Trojan Detection based on Delay Variations Measured using a High-Precision, Low-Overhead Embedded Test Structure, Symposium on Hardware-Oriented Security and Trust (HOST), 2012, pp. 75-82.

2011:

    * C. Lamech, R. Rad, M. Tehranipoor and J. Plusquellic, An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities, Transactions on Information Forensics and Security (TIFS), Volume: 6 , Issue: 3 , Part: 2, 2011, pp. 1170-1179.

    * C. Lamech, J. Aarestad, J. Plusquellic, R.M. Rad, K. Agarwal, REBEL and TDC: Embedded Test Structures for Regional Delay Measurements, International Conference on Computer-Aided Design, 2011, pp. 170-177.

    * C. Lamech, J. Aarested, K. Agarwal, J. Plusquellic, Characterizing Within-Die and Die-to-Die Delay Variations Introduced by Process Variations and SOI History Effect , Design Automation Conference (DAC), 2011, pp. 534-539.

    * J. Plusquellic, D. Acharyya, K. Agarwal, Measuring Spatial Variation Profile through Power Supply Current Measurements, International Symposium on Quality Electronic Design (ISQED), 2011, pp. 1-5.

    * K. Agarwal and J. Plusquellic, Minimally Invasive Methods for Characterizing Within-Die Variation, Invited presentation (and paper I thought) for Innovative IP Practice session called On-Chip Parametric Sensors, VLSI Test Symposium, 2011.

    * H. Salami, M. Tehranipoor, J. Plusquellic, A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time, Transactions on VLSI, Volume: PP, Issue: 99, 2011.

    * J. Plusquellic, D. Acharyya, K. Agarwal, Measuring Spatial Variation Profile through Power Supply Current Measurements, International Symposium on Quality Electronic Design (ISQED), 2011.

2010:

    * R. M. Rad, M. Tehranipoor, J. Plusquellic, A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans under Real Process and Environmental Conditions, Issue 99, Transactions in VLSI, 2009.
    Volume: 18, Issue: 12, pp. 1735-1744, 2010.

    * D. Acharyya, K. Agarwal, J. Plusquellic, Leveraging Existing Power Control Circuits and Power Delivery Architecture for Variability Measurement, International Test Conference, 2010.

    * J. Plusquellic and D. Acharyya, Leveraging the Power Grid for Localizing Trojans and Defects, International Symposium on Testing and Failure Analysis, 2010.

    * R. Helinski, D. Acharyya, J. Plusquellic, Quality Metric Evaluation of a Physical Unclonable Function Derived from an IC's Power Distribution System, Design Automation Conference, pp. 240-243, 2010.

    * V. Murray, G. A. Feucht, J. C. Lyke, M. Pattichis, J. Plusquellic, Cell-Based Architecture for Reconfigurable Wiring Manifolds, American Institute of Aeronautics and Astronautics, 2010.

    * J. Aarestad, D. Acharyya, R. Rad and J. Plusquellic, Detecting Trojans Though Leakage Current Analysis Using Multiple Supply Pad IDDQs, Transactions on Information Forensics and Security, Volume: 5, Issue: 4, pp. 893-904, 2010.

    * H. Salmani, M. Tehranipoor, J. Plusquellic, A Layout-aware Approach for Improving Localized Switching to Detect Hardware Trojans in Integrated Circuits, International Workshop on Information Forensics and Security, 2010.

2009:

    * K. Agarwal, D. Acharyya, J. Plusquellic, Characterizing Within-Die Variation from Multiple Supply Port IDDQ Measurements, International Conference on Computer-Aided Design, 2009, pp. 418-424.

    * R. Helinski, D. Acharyya, J. Plusquellic, A Physical Unclonable Function Defined Using Power Distribution System Equivalent Resistance Variations, Design Automation Conference, 2009, pp. 676-681.

    * R. M. Rad, J. Plusquellic, A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals, Journal of Electronic Testing, Theory and Applications, Volume 25, Numbers 2-3, June 2009.

    * R. M. Rad, J. Plusquellic, C. Patel , A. Singh Verification of Convolution Relation Between Sensitized Path's Gate Transients, Power Grid Impulse Responses and Power Port Transients, D3T Workshop, co-located with ITC, Nov. 2009.

    * J. Plusquellic, K. Agarwal, D. Acharyya Characterizing Within-Die Variation from Multiple Supply Port IDDQ Measurements, Design for Manufacturability and Yield Workshop, co-located with DAC, June 2009.

    * H. Salmani, M. Tehranipoor, J. Plusquellic New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time, 2nd International Workshop on Hardware-Oriented Security and Trust, co-located with DAC, June 2009.

2008:

    * R. M. Rad, X. Wang, M. Tehranipoor, J. Plusquellic, Power Supply Signal Calibration Techniques for Improving Detection Resolution to Hardware Trojans, International Conference on Computer-Aided Design, Nov., 2008, pp. 632-639.

    * W. Xiaoxiao, S. Hassan Salmani, M. Tehranipoor, J. Plusquellic, Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2008, pp. 87-95.

    * M. Itskovich, J. Plusquellic, IDDT Test Calibration Using a Programmable Processing Array, 4th Southern Conference on Programmable Logic, March, 2008, pp. 265-268.

    * Ryan Helinski, J. Plusquellic, Measuring Power Distribution System Resistance Variations, Transactions on Semiconductor Manufacturing, Volume 21, Issue 3, Aug. 2008, pp. 444-453.

    * W. Xiaoxiao, M. Tehranipoor, J. Plusquellic Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions, 1st International Workshop on Hardware-Oriented Security and Trust, co-located with DAC, June 2008, pp. 15-19.

    * R. Rad, J. Plusquellic, M. Tehranipoor Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals, 1st International Workshop on Hardware-Oriented Security and Trust, June 2008, pp. 3-7.

2007:

    * J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, Securing Designs Against Scan-Based Side-Channel Attacks, Transactions on Dependable and Secure Computing, Volume 4, Number 4, October-December 2007, pp. 325-336.

    * R. Helinski, J. Plusquellic and M. Tehranipoor, Detecting Small Delay Defects using Self-Relative Timing Bounds, Defect-based Testing Workshop, Nov. 2007.

    * R. MohammadPourrad and J. Plusquellic, Temporal Analysis and Spatial Deconvolution of Power Pad Transients Signals for Fault Localization , Defect-based Testing Workshop, Nov. 2007.

2006:

    * J. Plusquellic, D. Acharyya, M. Tehranipoor and C. Patel, Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results, International Symposium on Testing and Failure Analysis, Nov. 2006, pp. 36-45.

    * K. Agarwal, F. Liu, C. McDowell, S. Nassif, K. Nowka, M. Plamer, D. Acharyya, J. Plusquellic, A Test Structure for Characterizing Local Device Mismatches, Symposium on VLSI Circuits, June 2006, pp. 67-68.

    * J. Lee, M. Tehranipoor, J. Plusquellic, A Low-Cost Solution for Protecting IPs against Scan-Based Side-Channel Attacks, VLSI Test Symposium, May 2006, pp. 42-47.

    * J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method, Design and Test of Computers, Volume 23, Issue 4, April 2006, pp. 278-293.

    * A. Singh, J. Plusquellic, D. Phatak and C. Patel, Defect Simulation Methodology for iDDT Testing, Journal of Electronic Testing, Theory and Applications, Volume 22, Number 3, June 2006, pp. 255-272.

    * J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, Multiple Supply Pad IDDQ-based Defect Detection Techniques Applied to Hardware Test Chips, Defect Based Testing Workshop, Nov. 2006.

    * J. Lee, N. Ahmed, M. Tehranipoor, V. Jayaram and J. Plusquellic, A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG, North Atlantic Test Workshop, May 2006.

    * J. Plusquellic, D. Acharyya, M. Tehranipoor and C. Patel, Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs, North Atlantic Test Workshop, May 2006.

2005:

    * D. Acharyya and J. Plusquellic, Hardware Results Demonstrating Defect Detection using Power Supply Signal Measurements, VLSI Test Symposium, May 2005, pp. 433-438.

    * J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, Securing Scan Design Using Lock and Key Technique, International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2005, pp. 51-62.

    * C. Patel, A. Singh and J. Plusquellic, Defect Detection Using Quiescent Signal Analysis, Journal of Electronic Testing, Theory and Applications, Volume 21, Number 5, Oct. 2005, pp. 463-483.

    * S. Kamal Bahl, J. Plusquellic, and J. Thomas, A Comparative Study of W-CDMA Cell Search Designs, Journal of Circuits, Systems and Computers, Volume 14, Number 1, Feb. 2005, pp. 129-136.

    * N. Ahmed, C. P. Ravikumar, M. Tehranipoor and J. Plusquellic, At-Speed Transition Fault Testing with Low Speed Scan Enable, VLSI Test Symposium, May 2005, pp. 42-47 (BEST PAPER AWARD).

    * D. Acharyya, A. Singh, M. Tehranipoor, C. Patel and J. Plusquellic, Sensitivity Analysis of Quiescent Signal Analysis for Defect Detection, Defect Based Testing Workshop, May 2005, pp. 3-10.

2004:

    * D. Acharyya and J. Plusquellic, Hardware Results Demonstrating Defect Localization using Power Supply Signal Measurements, International Symposium on Testing and Failure Analysis, Nov. 2004, pp. 58-66.

    * A. Singh, C. Patel and J. Plusquellic, Fault Simulation Model for iDDT Testing: An Investigation, VLSI Test Symposium, April 2004, pp. 304-310.

    * A. Singh, C. Patel and J. Plusquellic, On-chip Impulse Response Generation for Analog and Mixed-signal Testing, International Test Conference, Oct. 2004, pp. 262-270.

    * C. Patel, A. Singh and J. Plusquellic, Defect Detection under Realistic Leakage Models using Multiple IDDQ Measurements, International Test Conference, Oct. 2004, pp. 319-328.

    * D. Acharyya and J. Plusquellic, Calibrating Power Supply Signal Measurements for Process and Probe Card Variations, Defect Based Testing Workshop, April 2004, pp. 23-30.

2003:

    * A. Singh, J. Tharian and J. Plusquellic, Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis, International Conference on Computer-Aided Design, Nov. 2003, pp. 748-753.

    * D. Acharyya and J. Plusquellic, Impedance Profile of Commercial Power Grid and Test System, International Test Conference, Oct. 2003, pp. 709-718.

    * J. Plusquellic and D. Phatak, Localizing Faults in Digital Chips using Steady-State Current Measurements, NASA Symposium on VLSI Design, May 2003.

    * A. Singh, D. S Phatak, T. Goff, M. Riggs, J. Plusquellic and C. Patel, Comparison of Branching CORDIC Implementations, International Conference on Application Specific Systems, Architectures and Processors, June 2003, pp. 215-225.

    * C. Patel, E. Staroswiecki, S. Pawar, D. Acharyya and J. Plusquellic, Defect Diagnosis using a Current Ratio based Quiescent Signal Analysis Model for Commercial Power Grids, Journal of Electronic Testing, Theory and Applications, Volume 19, Number 6, Dec. 2003, pp. 611-623.

    * D. S. Phatak, T. Goff and J. Plusquellic, IP-in-IP Tunneling to Enable the Simultaneous use of Multiple IP Interfaces for Network Level Connection Striping, Computer Networks: The International Journal of Computer and Telecommunications Networking, Volume 43, Issue 6, Dec. 2003, pp. 787-804.

    * J. Plusquellic, A. Singh, C. Patel and A. Gattiker, Power Supply Transient Signal Analysis for Defect-Oriented Test, Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 22, Issue 3, March 2003, pp. 370-374.

2002:

    * C. Patel, E. Staroswiecki, S. Pawar, D. Acharyya and J. Plusquellic, Diagnosis using Quiescent Signal Analysis on a Commercial Power Grid, International Symposium on Testing and Failure Analysis, Nov. 2002, pp. 713-722.

    * S. K. Bahl, J. Plusquellic, and J. Thomas, Comparison of Initial Cell Search Algorithms for W-CDMA Systems Using Cyclic and Comma Free Codes, Midwest Symposium on Circuits and System Conference, Volume 3, Aug. 2002, pp. 192-195.

    * A. Singh, J. Plusquellic and A. Gattiker, Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models, VLSI Test Symposium, May 2002, pp. 357-362.

    * C. Patel, E. Staroswiecki, D. Acharyya, S. Pawar, and J. Plusquellic, A Current Ratio Model for Defect Diagnosis using Quiescent Signal Analysis, Defect Based Testing Workshop, April 2002.

2001:

    * C. Patel, F. Muradali and J. Plusquellic, Power Supply Transient Signal Integration Circuit, International Test Conference, Nov. 2001, pp. 704-712.

    * A. Singh, C. Patel, S. Liao, J. Plusquellic and A. Gattiker, Detecting Delay Faults using Power Supply Transient Signal Analysis, International Test Conference, Nov. 2001, pp. 395-404.

    * C. Patel and J. Plusquellic, A Process and Technology-Tolerant IDDQ Method for IC Diagnosis, VLSI Test Symposium, May 2001, pp. 145-150.

    * J. Plusquellic, IC Diagnosis Using Multiple Supply Pad IDDQs Design and Test of Computers, Volume 18, Number 1, Jan. 2001, pp. 50-61.

2000:

    * J. Plusquellic, A. Germida, J. Hudson, E. Staroswiecki, C. Patel, Predicting Device Performance From Pass/Fail Transient Signal Analysis Data, International Test Conference, Oct. 2000, pp. 1070-1079.

    * A. Germida and J. Plusquellic, Detection of CMOS Defects under Variable Processing Conditions, VLSI Test Symposium, May 2000, pp. 195-201.

    * J. Plusquellic, C. Patel, and Y. Ouyang, Quiescent Signal Analysis for IC Diagnosis, System Test and Diagnosis Workshop, Oct. 2000.

1999:

    * J. Plusquellic, A. Germida and Z. Yan, 8-bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects, International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1999, pp. 68-76.

    * A. Germida, Z. Yan, J. Plusquellic and F. Muradali, Defect Detection using Power Supply Transient Signal Analysis, International Test Conference, Sept. 1999, pp. 67-76.

    * J. Plusquellic, D. M. Chiarulli, and S. P. Levitan, Time and Frequency Domain Transient Signal Analysis for Defect Detection in CMOS Digital ICs, Transactions on Circuits and Systems I, Volume 46, Issue 11, Nov. 1999, pp. 1390-1394.

1998:

    * J. Plusquellic, D. M. Chiarulli, and S. P. Levitan, Characterization of CMOS Defects using Transient Signal Analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1998, pp. 93-101.

    * J. Plusquellic, D. M. Chiarulli, and S. P. Levitan. An Automated Technique to Identify Defective CMOS Devices based on Linear Regression Analysis of Transient Signal Data, Workshop on IDDQ Testing, Nov. 1998, pp. 32-36.

1997:

    * J. Plusquellic, D. M. Chiarulli, and S. P. Levitan, Identification of Defective CMOS Devices using Correlation and Regression Analysis of Frequency Domain Transient Signal Data, International Test Conference, Nov. 1997, pp. 40-49.

1996:

    * J. Plusquellic, D. M. Chiarulli, and S. P. Levitan, Digital Integrated Circuit Testing using Transient Signal Analysis, International Test Conference, Oct. 1996, pp. 481-490.

1995:

    * J. Plusquellic, D. M. Chiarulli, and S. P. Levitan, Digital IC Device Testing by Transient Signal Analysis, Electronics Letters, Volume 31, Issue 18, Aug. 1995, pp. 1568-1570.